APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 66
APA600-CQ208B
Manufacturer Part Number
APA600-CQ208B
Description
FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
Manufacturer
Actel
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA600-CQ208B
Package
208CQFP
Family Name
ProASICPLUS
Device System Gates
600000
Number Of Registers
21504
Maximum Internal Frequency
180 MHz
Typical Operating Supply Voltage
2.5 V
Maximum Number Of User I/os
158
Ram Bits
129024
Re-programmability Support
Yes
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Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-29 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-53 • T
2 -5 6
Symbol t
CCYC
CMH
CML
OCA
OCH
RACH
RACS
RDCH
RDCS
RPCA
RPCH
ProASIC
PLUS
xxx
RDB, RBLKB
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= 0°C to 150°C, V
Clock high phase
Clock low phase
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
Old RPE valid from RCLKS ↑
Cycle time
New DO access from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
New RPE access from RCLKS ↑
RADDR
RCLKS
t RACS
RPE
DO
t RACH
t RDCH
t RDCS
Description
New Valid
DD
DD
Address
= 2.3 V to 2.7 V for Commercial/Industrial
= 2.3 V to 2.7 V for Military/MIL-STD-883
Cycle Start
t CMH
Old Data Out
t CCYC
v5.9
Min.
7.5
3.0
3.0
2.0
0.5
1.0
0.5
1.0
4.0
Old RPE Out
t CML
Max.
0.75
1.0
t OCH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t RPCA
New Valid Data Out
New RPE Out
t OCA
t RPCH
Notes
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