LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet
LPC2917_19_01
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LPC2917_19_01 Summary of contents
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LPC2917/2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — 9 December 2009 1. General description The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, CAN and LIN, 56 ...
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... Dual power supply: CPU operating voltage: 1.8 V ± I/O operating voltage: 2 3.6 V; inputs tolerant up to 5.5 V. 144-pin LQFP package. −40 °C to +85 °C ambient operating temperature range. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — 9 December 2009 © NXP B.V. 2009. All rights reserved. ...
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... LPC2919FBD144/01 3.1 Ordering options Table 2. Part options Type number Flash memory LPC2917FBD144/01 512 kB LPC2919FBD144/01 768 kB LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN SRAM SMC × TCM 32-bit × TCM 32-bit Rev. 03 — 9 December 2009 ...
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... ENCODER AHB TO APB CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2917/2919/01 block diagram LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ARM968E-S 1 × master 2 × ...
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... GPIO 0, pin 27 SCK2 [1] P0[28]/CAP0[0]/ 7 GPIO 0, pin 28 MAT0[0] [1] P0[29]/CAP0[1]/ 8 GPIO 0, pin 29 MAT0[ 3.3 V power supply for I/O DD(IO) LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN 1 LPC2917FBD144/01 LPC2919FBD144/01 36 002aae265 Function 1 Function 2 SPI2 SDI PWM2 CAP1 UART1 TXD CAN1 TXD UART1 RXD ...
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... GPIO 2, pin 27 MAT0[3]/EI7 [1] P1[27]/CAP1[2]/ 29 GPIO 1, pin 27 TRAP2/ PMAT3[3] [1] P1[26]/ 30 GPIO 1, pin 26 PMAT2[0]/ TRAP3/ PMAT3[2] LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function 1 SPI2 SCK SPI1 SCS0 SPI0 SCS3 SPI2 SCS1 - - SPI1 SCS1 SPI1 SCS2 TIMER0 CAP1 TIMER0 CAP0 SPI2 SCS0 ...
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... EI3/WE [1] P1[12]/SDA1/ 52 GPIO 1, pin 12 EI2/ 3.3 V power supply for I/O DD(IO) [1] P2[2]/MAT2[2]/ 54 GPIO 2, pin 2 TRAP1/D10 LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function 1 PWM1 MAT0 PWM0 MAT0 UART0 RXD UART0 TXD TIMER3 CAP3 TIMER3 CAP2 TIMER3 CAP1 TIMER3 CAP0 TIMER2 CAP3 TIMER2 CAP2 ...
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... P2[7]/MAT1[3]/ 79 GPIO 2, pin 7 EI3/D15 [1] P3[14]/SDI1/ 80 GPIO 3, pin 14 EI6/TXDC0 [1] P3[15]/SCK1/ 81 GPIO 3, pin 15 EI7/RXDC0 LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function 1 TIMER2 MAT3 SPI1 SCK SPI1 SDI SPI1 SCS0 SPI1 SDO TIMER1 MAT0 TIMER1 MAT1 SPI1 SDO SPI1 SCS0 SPI1 SCS3 SPI1 SCS2 ...
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... P2[13]/ 101 GPIO 2, pin 13 PMAT0[5]/ SDO0 [1] P0[4]/PMAT0[2]/ 102 GPIO 0, pin 4 D28 [1] P0[5]/PMAT0[3]/ 103 GPIO 0, pin 5 D29 V 104 3.3 V power supply for I/O DD(IO) LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function 1 CLK_OUT - SPI2 SCS1 SPI2 SCS3 EXTINT1 EXTINT0 - - QEI0 PHB QEI 0 PHA CLK_OUT - - - - - ...
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... V 128 ground for digital core SS(CORE) [1] P2[16]/TXD1/ 129 GPIO 2, pin 16 PCAP0[2]/BLS2 [1] P2[17]/RXD1/ 130 GPIO 2, pin 17 PCAP1[0]/BLS3 LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function ADC1 IN0 ADC1 IN1 ADC1 IN2 ADC1 IN3 I2C1 SDA I2C1 SCL TIMER3 MAT0 TIMER3 MAT1 ...
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... An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers • Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem). LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued Function 1 ...
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... ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit controller using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — ...
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... Both may be used for code and/or data storage. In addition SRAM for the ETB can be used as static memory for code and data storage. However, DMA access to this memory region is not supported. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — ...
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FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature ...
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... Table 5. Symbol JTAGSEL TRST TMS TDI TDO TCK 1. Only for 1.8 V power sources LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 8 for trip levels of the internal power-up reset circuit for characteristics of the several start-up and initialization times. Reset pin Direction Description IN external reset input, active LOW; pulled up internally IEEE 1149 ...
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... All branch clocks are outputs of the Power Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See more details of clock and power control within the device. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Power supply pins Description digital core supply 1 ...
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... GPDMA FLASH/SRAM/SMC general subsytem SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem GPIO0/1/2/3 TIMER 0/1/2/3 SPI0/1/2 UART0/1 WDT Fig 4. LPC2917/2919/01 block diagram, overview of clock areas LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 BA SE_ICLK0_CLK BASE_ICLK1_CLK BASE_IVNSS_CLK branch clocks branch clocks BASE_PCR_CLK branch clock BASE_MSCSS_CLK branch ...
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... Section 6.15.5 Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Table 8 contain an overview of all the base blocks in the LPC2917/2919/01 for more details of how to control the individual branch clocks. CGU0 generated base clock and branch clock overview Branch clock name ...
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... In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock source. See [4] The clock should remain activated when system wake-up on timer or UART is required. Table 8. Base clock BASE_OUT_CLK LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 CGU0 generated base clock and branch clock overview Branch clock name CLK_MSCSS_APB CLK_MSCSS_MTMR0 ...
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... When an AHB data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN init Rev. 03 — ...
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... The number of large sectors depends on the device type. A sector must be erased before data can be written to it. The flash memory also has sector-wise protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small sector contains 16 pages; a large sector contains 128 pages. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Table 9 ...
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... The minimum wait-states value can be calculated with the following formulas: Synchronous reading: t acc clk > ----------------- - WST t t tclk sys Asynchronous reading: t acc addr > --------------------- - WST t tclk sys LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Flash sector overview Sector size (kB ...
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... A separate chip select output is available for each bank. The chip select lines are configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory addressing. memory base addresses, chip selects, and bank internal addresses. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Table 11 shows how the 32-bit system address is mapped to the external bus Rev. 03 — ...
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... Clock description The External Static-Memory Controller is clocked by CLK_SYS_SMC, see 6.9.4 External memory timing diagrams A timing diagram for reading from external memory is shown in between the wait-state settings is indicated with arrows. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 External memory-bank address bit description Symbol Description BA[2:0] external static-memory base address (three most significant bits) ...
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... WSTWEN = 3, WST2 = 7 (1) BLS has the same timing configurations that use the byte lane enable signals to connect to write enable (8 bit devices). Fig 6. Writing to external memory LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN CLK(SYS) CS ...
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... DMA support for peripherals The GPDMA supports the following peripherals: SPI0/1/2 and UART0/1. The GPDMA can access both embedded SRAM blocks (16 kB and 32 kB), both TCMs, external static memory, and flash memory. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN ...
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... The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN 2 C-bus SCL pins plus three internal event sources ...
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... The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. Key features: • Internal chip reset if not periodically triggered • Timer counter register runs on always-on safe clock LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Event-router pin connections Direction Description IN ...
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... Four 32-bit match registers per timer that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6.15.4. 6.7.2. The register interface towards the system bus is clocked by Section Rev. 03 — ...
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... The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6.15.5 ...
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... Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep • Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces • Programmable data-frame size from bits LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Table 16 shows the UART pins (x runs from 0 to 1). UART pins ...
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... Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. [2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in slave mode. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 6.11.3. Table 17 shows the SPI pins (x runs from ...
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... LPC2917/2919/01. shows the GPIO pins. Table 18. Symbol GPIO0 pin[31:0] GPIO1 pin[31:0] GPIO2 pin[27:0] GPIO3 pin[15:0] LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6.7.2. Note that each SPI has its own CLK_SPIx branch clock for GPIO pins Pin name Direction ...
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... The two CAN controllers in the LPC2917/2919/01 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2917/2919/01. shows the CAN pins (x runs from 0 to 1). Table 19. Symbol CANx TXD CANx RXD LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 CAN pins Pin name Direction Description ...
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... The main features if the I • and I and do not support powering off of individual devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 LIN controller pins Pin name Direction Description TXDL0/1 OUT LIN channel 0/1 transmit data output ...
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... Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 C-bus can be used for test and diagnostic purposes. ...
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... To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section 6.15.2. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — 9 December 2009 © ...
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... NXP Semiconductors capture MSCSS TIMER0 capture PAUSE MSCSS TIMER1 Fig 8. Modulation and Sampling Control Subsystem (MSCSS) block diagram LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 AHB-TO-APB BRIDGE MSCSS QEI start ADC1 start ADC2 start PWM0 carrier synch carrier PWM1 carrier synch ...
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... Optional compare condition to generate a ‘less than’ ‘equal to or greater than’ compare-value indication for each channel • Power-down mode LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6.14.4.2. Pins connected to the four PWM modules are described in Rev. 03 — 9 December 2009 ARM9 microcontroller with CAN and LIN © ...
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... The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2917/2919/01. The VREFN and VREFP pins are common for both ADCs. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Figure 9, shows the basic architecture of each ADC ...
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... Interrupt generation on match event, capture event, PWM counter overflow or trap event • A burst mode mixing the external carrier signal with internally generated PWM • Programmable sync-delay output to trigger other PWM modules (master/slave behavior) LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Analog to digital converter pins Pin name Direction IN1/2[7:0] ...
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... BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective. The actual PWM and prescale counters are located in the PWM domain but system control takes place in the APB domain. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ...
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... PWMn CAP[1] PWMn CAP[2] PWMn MAT[0] PWMn MAT[1] PWMn MAT[2] PWMn MAT[3] PWMn MAT[4] PWMn MAT[5] PWMn TRAP LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6.15 for details of the connections of the PWM modules within the MSCSS in the PWM pins Pin name Direction PCAPn[0] ...
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... In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section 6 ...
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... The Power, Clock, and Reset Control Subsystem (PCRSS) in the LPC2917/2919/01 includes the Clock Generator Units (CGU0 and CGU1), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). Figure 11 communication with the AHB system bus. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 QEI pins Pin name ...
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... AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 CGU0 PLL ...
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... BASE_MSCSS_CLK 5 BASE_UART_CLK 6 BASE_ICLK0_CLK 7 BASE_SPI_CLK 8 BASE_TMR_CLK 9 BASE_ADC_CLK 10 reserved 11 BASE_ICLK1_CLK [1] Maximum frequency that guarantees stable operation of the LPC2917/2919/01. [2] Fixed to low-power oscillator. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 CGU0 base clocks Frequency [1] (MHz) 0.4 125 [2] 0.4 125 125 125 125 50 125 4.5 - 125 Rev. 03 — 9 December 2009 ...
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... The crystal oscillator can be used as source for high-frequency clocks external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 FDIV0 ...
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... Clock Activity Detection: and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 For every output generator generating the base clocks a ...
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... The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock. 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN ...
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... LOCK signal high once it has regained lock on the input clock. 6.15.2.3 Pin description The CGU0 module in the LPC2917/2919/01 has the pins listed in Table 27. Symbol XOUT_OSC XIN_OSC LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 PSEL bits / 2PDIV bypass / MDIV MSEL bits ...
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... The key features of the Reset Generation Unit (RGU) are: • Reset controlled individually per subsystem • Automatic reset stretching and release • Monitor function to trace resets back to source LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Section (CGU1) FDIV0 AHB TO DTL BRIDGE CGU1 pins ...
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... QEI_RST DMA_RST VIC_RST AHB_RST 6.15.4.2 Pin description The RGU module in the LPC2917/2919/01 has the following pins. RGU pins. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Reset output configuration Reset source power-on reset module POR_RST, RST pin RGU_RST, WATCHDOG PCR internal; is source for COLD_RST ...
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... CGU0). Table 31 shows the relation between branch and base clocks, see also Every branch clock is related to one particular base clock not possible to switch the source of a branch clock in the PMU. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 RGU pins Direction ...
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... CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK CLK_MSCSS_ADC2_APB BASE_MSCSS_CLK CLK_MSCSS_QEI LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Branch clock overview Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK ...
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... The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: • Target 0 is ARM processor FIQ (fast interrupt service). • Target 1 is ARM processor IRQ (standard interrupt service). LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Branch clock overview …continued Base clock ...
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... Testing RTOS (Real-Time Operating System) interrupt handling without using device-specific interrupt service routines. • Software emulation of an interrupt-requesting device, including interrupts. 6.16.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Section 6.7.2. ...
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... I LOW-level short-circuit OLS output current General T storage temperature stg T ambient temperature amb LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Conditions average value per supply pin average value per ground pin [3][4][5] [4][5] for ADC1/2: I/O port 0 pin 8 to pin 23 ...
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... Note that pull-up should be off. With pull-up do not exceed 3.6 V. [6] 112 mA per should not be exceeded. DD(IO) SS(IO) [7] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Conditions on all pins human body model charged device model on corner pins charged device model ...
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... Input pins and I/O pins configured as input V input voltage I V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN = 3 3 DDA(ADC3V3) Conditions Min 1.71 Device state after reset; - system clock °C; ...
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... C is crystal load capacitance and C xtal [7] This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/ DDA(ADC3V3) Conditions all port pins 3.3 V; ...
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... T ADC and the ideal transfer curve. See [8] See Figure 16. ADC IN[y] Fig 16. Suggested ADC interface - LPC2917/2919/01 ADC1/2 IN[y] pin LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 for 2 μs before reset is de-asserted; V must be above V DD(CORE) trip(high) − ° ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 (2) (5) (4) (3) 1 LSB (ideal) 1018 ...
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... Fig 18 DD(CORE) (mA Conditions: T but not configured to run. Fig 19. I LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/ °C; active mode entered executing code from flash; core voltage 1.8 V; all amb at different core frequencies (active mode) DD(CORE) 125 MHz ...
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... NXP Semiconductors I DD(CORE) (mA) Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 20. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 80 125 MHz 60 100 MHz 80 MHz 40 40 MHz 20 10 MHz 0 −40 − different temperatures (active mode) DD(CORE) Rev. 03 — ...
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... V OL (mV) 400 300 200 100 V Fig 21. Typical LOW-level output voltage versus LOW-level output current 3 (V) 3.0 2.5 2.0 V Fig 22. Typical HIGH-level output voltage versus HIGH-level output current LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 85 °C 25 °C 0 °C −40 °C 0 1.0 2.0 3.0 = 3.3 V. DD(IO) 1.0 2.0 3.0 = 3.3 V. DD(IO) Rev. 03 — 9 December 2009 ...
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... V Fig 23. Typical pull-down current versus temperature −20 I I(pu) (μA) −40 −60 −80 −100 V Fig 24. Typical pull-up current versus temperature LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 −40 − 3 DD(IO) −40 − Rev. 03 — 9 December 2009 ARM9 microcontroller with CAN and LIN ...
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... PLL f PLL input frequency i(PLL) f PLL output frequency o(PLL) t clock access time a(clk) t address access time a(A) LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN = 3 3.6 V; all voltages are measured with respect to DDA(ADC3V3) [1] Conditions Min ...
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... Fig 25. Low-power ring oscillator thermal characteristics LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 …continued = 3 3.6 V; all voltages are measured with respect to DDA(ADC3V3) [1] Conditions on CAN TXDC pin = 25 °C (final testing). Both pre-testing and final testing use correlated amb − ...
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... Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. shifting edges SCKn SDOn SDIn Fig 26. SPI data input set-up time in SSP Master mode LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 2 C-bus interface 2 C-bus pins = 3 3.6 V ...
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... Number of program/erase cycles. Table 39 -40 amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Flash characteristics ° ° + DD(CORE) DD(OSC_PLL 3.6 V; all voltages are measured with respect to ground. Parameter Conditions endurance retention time powered ...
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... When the byte lane select signals are used to connect the write enable input (8 bit devices), t [3] When the byte lane select signals are used to connect the write enable input (8 bit devices), t [4] For 16 and 32 bit devices. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN = 3 3.6 V; all voltages are measured with respect to ...
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... NXP Semiconductors CSLOEL OE/BLS Fig 27. External memory read access CS BLS Fig 28. External memory write access LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t t CSLWEL ...
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... LPC2917/2919/01 by controlling the temperature and the core voltage accordingly. 145 core frequency (MHz) 135 125 115 105 Fig 29. Core operating frequency versus temperature for different core voltages LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/ 3.6 V; all voltages are measured with respect to DDA(ADC3V3) Conditions f = 4.5 MHz; i(ADC) f ...
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... Fig 30. Core operating frequency versus core voltage for different temperatures 10.2 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 31. SPI timing in master mode LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 25 °C 45 °C 65 °C 85 °C 1.65 1.75 SDOn MSB OUT ...
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... NXP Semiconductors SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 32. SPI timing in slave mode LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 SDIn MSB IN SDOn MSB OUT SDIn MSB IN DATA VALID SDOn MSB OUT DATA VALID Rev. 03 — 9 December 2009 ARM9 microcontroller with CAN and LIN ...
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... Loops must be made as small as possible, in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C smaller accordingly to the increase in parasitics of the PCB layout. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN ...
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... Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT486-1 136E23 Fig 34. Package outline SOT486-1 (LQFP144) LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/ ...
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... Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Rev. 03 — 9 December 2009 © ...
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... Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 and 43 SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) ...
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... MSL: Moisture Sensitivity Level Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN maximum peak temperature ...
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... CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — LIN specification package, revision 2.0 LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 Abbreviations list Description Advanced High-performance Bus Advanced Microcontroller Bus Architecture ...
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... LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN Data sheet status Change notice Product data sheet - Preliminary data sheet - Preliminary data sheet - Rev. 03 — 9 December 2009 Supersedes LPC2917_19_01_2 LPC2917_19_01_1 - © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 [3] Definition This document contains data from the objective specification for product development. ...
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... Clock description . . . . . . . . . . . . . . . . . . . . . . 27 6.11 General subsystem 6.11.1 General subsystem clock description . . . . . . . 27 6.11.2 Chip and feature identification . . . . . . . . . . . . 27 6.11.3 System Control Unit (SCU 6.11.4 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.11.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 28 LPC2917_19_01_3 Product data sheet LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN 6.12 Peripheral subsystem . . . . . . . . . . . . . . . . . . 28 6.12.1 Peripheral subsystem clock description 6.12.2 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 28 6.12.2.1 Functional description . . . . . . . . . . . . . . . . . . 29 6.12.2.2 Clock description ...
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... NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ARM9 microcontroller with CAN and LIN Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Contact information . . . . . . . . . . . . . . . . . . . . 84 Contents All rights reserved. Date of release: 9 December 2009 Document identifier: LPC2917_19_01_3 ...