LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 46

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_01_3
Product data sheet
Fig 11. Power, Clock, and Reset control Sub System (PCRSS) block diagram
AHB2DTL
BRIDGE
6.15.1 Clock description
OSCILLATOR
LOW POWER
OSCILLATOR
REGISTERS
REGISTERS
EXTERNAL
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
CGU0/1
RING
RGU
POR
FDIV[6:0]
PLL
RESET OUTPUT
DELAY LOGIC
DEGLITCH/
INPUT
SYNC
Rev. 03 — 9 December 2009
Section
OUT11
OUT6
OUT0
OUT1
OUT5
OUT7
OUT9
CGU0
RGU
6.7.2. CLK_SYS_PCRSS is derived from
LPC2917/01; LPC2919/01
FDIV
PLL
ARM9 microcontroller with CAN and LIN
OUT
CGU1
PCR_RST
reset from watchdog counter
WARM_RST
COLD_RST
RGU_RST
POR_RST
AHB_RST
SCU_RST
RST (device pin)
REGISTERS
CONTROL
ENABLE
CLOCK
GATES
CLOCK
PMU
© NXP B.V. 2009. All rights reserved.
PMU
wakeup_a
002aae355
disable:
grant
master
request
branch
clocks
AHB
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