LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 15

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
1.
LPC2917_19_01_3
Product data sheet
Only for 1.8 V power sources
6.6.1 Reset and power-up behavior
6.6.2 Reset strategy
6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
6.6 Reset, debug, test, and power description
The LPC2917/2919/01 contains external reset input and internal power-up reset circuits.
This ensures that a reset is extended internally until the oscillators and flash have reached
a stable state. See
Section 9
the reset pin.
Table 4.
At activation of the RST pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/2919/01 is assumed to be connected to debug hardware, and internal
circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead
of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
The LPC2917/2919/01 contains a central module, the Reset Generator Unit (RGU) in the
Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals
towards the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
The LPC2917/2919/01 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
pins can be used to connect a debugger probe for the embedded ARM processor. Pin
JTAGSEL selects between boundary-scan mode and debug mode.
boundary- scan test pins.
Table 5.
Symbol
RST
Symbol
JTAGSEL
TRST
TMS
TDI
TDO
TCK
for characteristics of the several start-up and initialization times.
Reset pin
IEEE 1149.1 boundary-scan test and debug interface
Direction
IN
Description
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan and flash programming; pulled up internally
test reset input; pulled up internally (active LOW)
test mode select input; pulled up internally
test data input, pulled up internally
test data output
test clock input
Section 8
Rev. 03 — 9 December 2009
external reset input, active LOW; pulled up internally
Description
for trip levels of the internal power-up reset circuit
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
Table 5
© NXP B.V. 2009. All rights reserved.
Table 4
shows the
1
. See
shows
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