LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 41

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_01_3
Product data sheet
6.14.4.3 Clock description
6.14.5 Pulse Width Modulator (PWM)
Table 22.
Remark: Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see
Table
The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and
CLK_ADCx (x = 1 or 2), see
and CLK_MSCSS_ADCx_APB branch clocks for power management. If an ADC is
unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off.
The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to
CLK_MSCSS_APB since they are derived from the same base clock
BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical
since they are derived from the same base clock BASE_ADC_CLK.
The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.
Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also
Figure
The MSCSS in the LPC2917/2919/01 includes four PWM modules with the following
features.
Symbol
ADC1/2 IN[7:0]
ADCn_EXT_START CAP1[n]
VREFN
VREFP
•
•
•
•
•
•
•
•
•
•
Six pulse-width modulated output signals
Double edge features (rising and falling edges programmed individually)
Optional interrupt generation on match (each edge)
Different operation modes: continuous or run-once
16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods
A protective mode (TRAP) holding the output in a software-controllable state and with
optional interrupt generation on a trap event
Three capture registers and capture trigger pins with optional interrupt generation on
a capture event
Interrupt generation on match event, capture event, PWM counter overflow or trap
event
A burst mode mixing the external carrier signal with internally generated PWM
Programmable sync-delay output to trigger other PWM modules (master/slave
behavior)
33) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant.
9.
Analog to digital converter pins
Pin name
IN1/2[7:0]
VREFN
VREFP
Rev. 03 — 9 December 2009
Section
Direction
IN
IN
IN
IN
LPC2917/01; LPC2919/01
6.7.2. Note that each ADC has its own CLK_ADCx
Description
analog input for 3.3 V ADC1/2, channel 7 to
channel 0
ADC external start-trigger input (n = 1 or 2)
ADC LOW reference level
ADC HIGH reference level
ARM9 microcontroller with CAN and LIN
© NXP B.V. 2009. All rights reserved.
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