LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 4
LPC2917_19_01
Manufacturer Part Number
LPC2917_19_01
Description
The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2917_19_01.pdf
(86 pages)
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4. Block diagram
LPC2917_19_01_3
Product data sheet
Fig 1.
TIMER0/1 MTMR
ACCEPTANCE
QUADRATURE
MANAGEMENT
3.3 V ADC1/2
PWM0/1/2/3
GENERATION
UNIT CGU0/1
GENERATION
ENCODER
Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA.
LPC2917/2919/01 block diagram
GLOBAL
FILTER
POWER
CAN0/1
LIN0/1
I
CLOCK
RESET
2
LPC2917/01
LPC2919/01
UNIT
C0/1
UNIT
CONTROLLER
INTERRUPT
VECTORED
AHB TO DTL
AHB TO APB
AHB TO APB
AHB TO DTL
BRIDGE
BRIDGE
BRIDGE
BRIDGE
1 × master
2 × slave
ITCM
16 kB
slave
slave
slave
slave
Rev. 03 — 9 December 2009
TEST/DEBUG
ARM968E-S
INTERFACE
8 kB SRAM
MATRIX
LAYER
MULTI
interface
AHB
JTAG
master
master
slave
slave
slave
slave
slave
slave
slave
LPC2917/01; LPC2919/01
DTCM
16 kB
EMBEDDED SRAM 16 kB
EMBEDDED SRAM 32 kB
MEMORY CONTROLLER
AHB TO APB
AHB TO APB
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
BRIDGE
BRIDGE
EXTERNAL STATIC
512/768 kB
ARM9 microcontroller with CAN and LIN
SYSTEM CONTROL
GENERAL PURPOSE I/O
CHIP FEATURE ID
EEPROM
EVENT ROUTER
16 kB
RS485 UART0/1
PORTS 0/1/2/3
TIMER 0/1/2/3
SPI0/1/2
WDT
© NXP B.V. 2009. All rights reserved.
002aad959
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