LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 18

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_01_3
Product data sheet
6.7.2 Base clock and branch clock relationship
Table 7
and their derived branch clocks. In relevant cases more detailed information can be found
in the specific subsystem description. Some branch clocks have special protection since
they clock vital system parts of the device and should (for example) not be switched off.
See
Table 7.
Base clock
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
Section 6.15.5
and
CGU0 generated base clock and branch clock overview
Table 8
for more details of how to control the individual branch clocks.
contain an overview of all the base blocks in the LPC2917/2919/01
Rev. 03 — 9 December 2009
Branch clock name
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_PCR_SLOW
CLK_IVNSS_APB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
Parts of the device clocked
by this branch clock
watchdog timer
ARM968E-S and TCMs
AHB bus infrastructure
AHB side of bridge in PCRSS
Flash-Memory Controller
Embedded SRAM Controller 0
(32 kB)
Embedded SRAM Controller 1
(16 kB)
External Static-Memory
Controller
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 2
GPIO bank 3
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
GPDMA
PCRSS, CGU, RGU and PMU
logic clock
APB side of the IVNSS
CAN controller Acceptance
Filter
CAN channel 0
CAN channel 1
I2C0
I2C1
LIN channel 0
LIN channel 1
© NXP B.V. 2009. All rights reserved.
Remark
[1]
[2] [4]
[1]
,
18 of 86
[3]