LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 23

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_01_3
Product data sheet
6.8.6 EEPROM
6.9.1 Description
6.9 External static memory controller
Remark: If the programmed number of wait-states is more than three, flash-data reading
cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative
reading is active.
EEPROM is a non-volatile memory mostly used for storing relatively small amounts of
data, for example for storing settings. It contains one 16 kB memory block and is
byte-programmable and byte-erasable.
The EEPROM can be accessed only through the flash controller.
The LPC2917/2919/01 contains an external Static Memory Controller (SMC) which
provides an interface for external (off-chip) memory devices.
Key features are:
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing.
memory base addresses, chip selects, and bank internal addresses.
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Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices.
Asynchronous page-mode read operation in non-clocked memory subsystems.
Asynchronous burst-mode read access to burst-mode ROM devices.
Independent configuration for up to eight banks, each up to 16 MB.
Programmable bus-turnaround (idle) cycles (one to 16).
Programmable read and write wait states (up to 32), for static RAM devices.
Programmable initial and subsequent burst-read wait state for burst-ROM devices.
Programmable write protection.
Programmable burst-mode operation.
Programmable external data width: 8 bits, 16 bits or 32 bits.
Programmable read-byte lane enable control.
Table 11
shows how the 32-bit system address is mapped to the external bus
Rev. 03 — 9 December 2009
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
© NXP B.V. 2009. All rights reserved.
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