LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 62

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[8]
Table 34.
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC2917_19_01_3
Product data sheet
Symbol
V
V
Z
V
C
E
E
E
E
E
R
DDA(ADC3V3)
Fig 16. Suggested ADC interface - LPC2917/2919/01 ADC1/2 IN[y] pin
i
VREFN
VREFP
IA
D
L(adj)
O
G
T
ia
vsi
The power-up reset has a time filter: V
V
Conditions: V
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral non-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
ADC and the ideal transfer curve. See
See
trip(low)
Figure
for 11 μs before internal reset is asserted.
ADC static characteristics
= 3.0 V to 3.6 V; T
Parameter
voltage on pin VREFN
voltage on pin VREFP
input impedance
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
voltage source interface
resistance
16.
SS(IO)
Figure
G
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
= 0 V, V
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
17.
DDA(ADC3V3)
L(adj)
ADC IN[y]
amb
D
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
) is the difference between the actual step width and the ideal step width. See
=
SAMPLE
−
DD(CORE)
40
Figure
= 3.3 V.
°
C to +85
Conditions
between V
V
VREFP
17.
must be above V
LPC2XXX
Rev. 03 — 9 December 2009
V
3 pF
SS(IO),
°
Figure
C unless otherwise specified; ADC frequency 4.5 MHz.
VREFN
20 kΩ
V
SS(CORE)
17.
and
trip(high)
Figure
5 pF
LPC2917/01; LPC2919/01
for 2 μs before reset is de-asserted; V
17.
[1][2][3]
[1][4]
[1][5]
[1][6]
[1][7]
[8]
ADC IN[y]
ARM9 microcontroller with CAN and LIN
Min
0
V
4.4
V
-
-
-
-
-
-
VREFN
VREFN
R vsi
+ 2 -
Typ
-
-
-
-
-
-
-
-
-
-
002aae280
V EXT
Max
V
V
-
V
1
±1
±2
±3
±0.5
±4
40
VREFP
DDA(ADC3V3)
VREFP
DD(CORE)
Figure
© NXP B.V. 2009. All rights reserved.
− 2
17.
must be below
Unit
V
V
kΩ
V
pF
LSB
LSB
LSB
%
LSB
kΩ
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