LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 27

• Manufacturer Part Number: LPC2917_19_01
• Description: The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_01_3
Product data sheet
6.10.2 Clock description
6.11.1 General subsystem clock description
6.11.2 Chip and feature identification
6.11.3 System Control Unit (SCU)
6.11.4 Event router
6.11 General subsystem
The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see
Section
The general subsystem is clocked by CLK_SYS_GESS, see
The Chip/Feature ID (CFID) module contains registers which show and control the
functionality of the chip. It contains an ID to identify the silicon and also registers
containing information about the features enabled or disabled on the chip.
The key features are:
The CFID has no external pins.
The system control unit contains system-related functions.The key feature is configuration
of the I/O port-pins multiplexer. It defines the function of each I/O pin of the
LPC2917/2919/01. The I/O pin configuration should be consistent with peripheral function
usage.
The SCU has no external pins.
The event router provides bus-controlled routing of input events to the vectored interrupt
controller for use as interrupt or wake-up signals.
Key features:
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
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Identification of product
Identification of features enabled
Up to 19 level-sensitive external interrupt pins, including the receive pins of SPI, CAN,
LIN, and UART, as well as the I
Input events can be used as interrupt source either directly or latched
(edge-detected).
Direct events disappear when the event becomes inactive.
Latched events remain active until they are explicitly cleared.
Programmable input level and edge polarity.
Event detection maskable.
Event detection is fully asynchronous, so no clock is required.
6.7.2.
Rev. 03 — 9 December 2009
2
LPC2917/01; LPC2919/01
C-bus SCL pins plus three internal event sources.
ARM9 microcontroller with CAN and LIN
Section
6.7.2.
© NXP B.V. 2009. All rights reserved.
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