LPC2917_19_01 NXP Semiconductors, LPC2917_19_01 Datasheet - Page 11

The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel

LPC2917_19_01

Manufacturer Part Number
LPC2917_19_01
Description
The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial andparallel
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 3.
[1]
[2]
[3]
6. Functional description
LPC2917_19_01_3
Product data sheet
Pin name
V
P0[18]/IN2[2]/
PMAT2[0]/A14
P0[19]/IN2[3]/
PMAT2[1]/A15
P3[4]/MAT3[2]/
PMAT2[4]/
TXDC1
P3[5]/MAT3[3]/
PMAT2[5]/
RXDC1
P2[18]/SCS2[1]/
PCAP1[1]/D16
P2[19]/SCS2[0]/
PCAP1[2]/D17
P0[20]/IN2[4]/
PMAT2[2]/A16
P0[21]/IN2[5]/
PMAT2[3]/A17
P0[22]/IN2[6]/
PMAT2[4]/A18
V
P0[23]/IN2[7]/
PMAT2[5]/A19
P2[20]/
PCAP2[0]/D18
TDI
DD(IO)
SS(IO)
Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5V tolerant; TTL with hysteresis; programmable pull-up /
pull-down / repeater.
Analog pad; analog I/O
Analog pad.
LQFP144 pin assignment
Pin
131
132
133
134
135
136
137
138
139
140
141
142
143
144
6.1 Architectural overview
[3]
[3]
[1]
[1]
[1]
[1]
[3]
[3]
[3]
[3]
[1]
[1]
The LPC2917/2919/01 consists of:
Description
Default function
3.3 V power supply for I/O
GPIO 0, pin 18
GPIO 0, pin 19
GPIO 3, pin 4
GPIO 3, pin 5
GPIO 2, pin 18
GPIO 2, pin 19
GPIO 0, pin 20
GPIO 0, pin 21
GPIO 0, pin 22
ground for I/O
GPIO 0, pin 23
GPIO 2, pin 20
IEEE 1149.1 data in, pulled up internally
An ARM968E-S processor with real-time emulation support
An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
…continued
Rev. 03 — 9 December 2009
Function 1
ADC2 IN2
ADC2 IN3
TIMER3 MAT2
TIMER3 MAT3
SPI2 SCS1
SPI2 SCS0
ADC2 IN4
ADC2 IN5
ADC2 IN6
ADC2 IN7
SPI2 SDO
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
Function 2
PWM2 MAT0
PWM2 MAT1
PWM2 MAT4
PWM2 MAT5
PWM1 CAP1
PWM1 CAP2
PWM2 MAT2
PWM2 MAT3
PWM2 MAT4
PWM2 MAT5
PWM2 CAP0
Function 3
EXTBUS A14
EXTBUS A15
CAN1 TXD
CAN1 RXD
EXTBUS D16
EXTBUS D17
EXTBUS A16
EXTBUS A17
EXTBUS A18
EXTBUS A19
EXTBUS D18
© NXP B.V. 2009. All rights reserved.
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