M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 104

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 1.93: Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Signal conductor level
(Note 1)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
RxD
Signal conductor level
(Note 1)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
TxD
RxD
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
2
2
2
2
Note: Equal in waveform because TxD
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Start
ST
ST
Start
ST
ST
bit
bit
D
D
D
D
Data is set in UARTi transmit buffer register
0
0
0
0
D
D
D
D
1
1
1
1
Tc
Tc
D
D
D
D
2
2
2
2
D
D
2
D
D
3
3
and RxD
3
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
2
D
D
are connected.
Transferred from UARTi transmit buffer register to UARTi transmit register
D
D
6
6
6
6
D
D
D
D
Parity
Parity
1-104
7
7
7
7
bit
bit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
P
P
P
P
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
SP
SP
SP
fi : frequency of BRGi count source (f
f
n : value set to BRGi
fi : frequency of BRGi count source (f
f
n : value set to BRGi
EXT
EXT
Stop
Stop
bit
bit
Read to receive buffer
: frequency of BRGi count source (external clock)
: frequency of BRGi count source (external clock)
The level is detected by the
interrupt routine.
ST
ST
ST
ST
A “L” level returns from TxD
the occurrence of a parity error.
A “L” level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
EXT
EXT
D
D
D
D
3
3
3
3
Mitsubishi microcomputers
D
D
D
D
M30240 Group
4
4
4
4
1
1
D
D
D
, f
D
, f
5
5
5
5
8
2
8
2
, f
, f
due to
D
D
due to
D
D
32
32
6
6
6
6
)
)
D
D
D
D
7
7
7
7
P
P
P
P
Read to receive buffer
SP
SP
SP
SP
The level is
detected by the
interrupt routine.