M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 60

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Specifications in this manual are tentative and subject to change
Universal Serial Bus
Figure 1.47: USB Endpoint x IN CSR
2.18.4.16 USB Endpoint x OUT Control and Status Register
The CPU writes a “1” to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes
the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be
flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredict-
able results.
When the CPU sets this bit to a “1”, the IN_PKT_RDY bit is set automatically by the USB FCU after the number
of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see “IN (Transmit)
FIFO” operation for details).
The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.48 contains control and sta-
tus information of the respective OUT endpoint 1-4.
• OUTxCSR0 (OUT_PKT_RDY):
The OUTxCSR0 bit for the OUT FIFO status (see “OUT (Receive) FIFOs” for details).
The USB FCU sets this bit to a “1” and updates the FIFO pointers after a data packet has been successfully
received from the host. The CPU writes a “0” to this bit to inform the USB FCU that a data packet has been
unloaded. The USB FCU updates the FIFO pointers when this occurs. The CPU must allow at least one clock
cycle between writing and reading bit OUTxCSR0.
• OUTXxCSR1 (OVER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets
this bit to a “1” at the beginning of an OUT token when two data packets are already present in the FIFO. Set-
ting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear
OUTXCSR1.
• OUTxCSR2 (SEND_STALL):
The CPU writes a “1” to this bit when the endpoint is stalled. The USB FCU returns a STALL handshake while
this bit is set. The CPU writes a “0” to clear this bit.
• OUTxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration
of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a “1”, the device accepts either DATA0 or
DATA1 for the PID sent by the host.
USB Endpoint x IN Control and Status Register (Note 5)
b7
•INxCSR7 (AUTO_SET):
b6
b5
b4
b3
b2
b1
b0
Note 1: Write "1" only or read
Note 2: Write "0" only or read
Note 3: Read only
Note 4: Write only - Read "0"
Note 5: Refer to section 5.5 "Programming Notes" for this register
Bit symbol
INxCSR0
INxCSR1
INxCSR2
INxCSR3
INxCSR4
INxCSR5
INxCSR6
INxCSR7
Symbol
EPiICS (i= 1-4)
IN_PKT_RDY Bit
UNDER_RUN Flag
SEND_STALL Bit
ISO Bit
INTPT
TX_NOT_EPT Flag
FLUSH Bit
AUTO_SET Bit
Bit name
0319
1-60
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16,
0321
Address
0 : Not ready
1 : Ready
0 : No FIFO underrun
1 : FIFO underrun has occured
0 : No action
1 : Stall IN Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
0 : Transmit FIFO is empty
1 : Transmit FIFO is not empty
0 : No action
1 : Flush the FIFO
0 : AUTO-SET disabled
1 : AUTO-SET enabled
16,
0329
16,
0331
16
Mitsubishi microcomputers
Function
When reset
00
M30240 Group
16
R
Note 1
Note 3
Note 4
Note 2
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
W