M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 66

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Specifications in this manual are tentative and subject to change
DMAC
Table 1.15:
Table 1.16:
2.19.1 Transfer cycle
2.19.2 DMAC transfer cycles
16-bit transfers
Internal ROM/
RAM No wait
8-bit transfers
Transfer unit
(DMBIT=”1”)
(DMBIT=”0”)
2.19.1.1 Effect of source and destination addresses
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses
and the software waits are inserted.
Any combination of even or odd transfer read and write addresses is possible. Table 1.15 show the
number of DMAC transfer cycles. Table 1.16 shows the corresponding coefficient values. Figure 1.57
shows an example of the transfer cycle for a source read.
The number of DMAC transfer cycles can be calculated as follows:
1
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd address-
es, there is one more source read cycle and destination write cycle than when the source and destination both
start at even addresses.
Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k
Number of DMAC transfer cycles
Coefficients j,k
Internal memory
address
Internal ROM/
RAM with wait
Access
Even
Even
Odd
Odd
2
read cycles
Number of
1
1
1
2
Single-chip mode
SFR area
2
write cycles
Number of
1-66
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1
1
1
2
Mitsubishi microcomputers
M30240 Group