M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 35

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
NMI Interrupt
Table 1.11:
2.13 NMI Interrupt
Reset
NMI
DBC
Watchdog timer
Single step
Address match
Software interrupt
2.14.3 Flag changes
2.13.1 Notes:
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI
interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit
5 at address 03F0
This pin cannot be used as a normal port input.
(1)
(2)
When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and
the processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of
the received interrupt. However, when interrupt requests are received for software interrupts 32 to 63,
the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer
select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does
not change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in
the case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow,
and undefined instruction interrupts. Table 1.11 shows how the IPL changes when interrupt requests
are received.
When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the
NMI interrupt is non-maskable, it cannot be disabled.
When the NMI pin input is “L”, do not set the microcomputer in stop mode or wait mode. The NMI
interrupt is triggered by the falling edge, so the “L” level does not need to be maintained longer
than necessary.
Interrupt
Change of IPL state when interrupt request are accepted
16
).
Level 0 (“000
Level 7 (“111
Does not change
Level 7 (“111
Does not change
Does not change
Does not change
2
2
2
), is set
), is set
), is set
1-35
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Change of IPL
Mitsubishi microcomputers
M30240 Group