M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 94
M30240ECFP
Manufacturer Part Number
M30240ECFP
Description
M30240 Group Specification
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M30240ECFP.pdf
(142 pages)
- Current page: 94 of 142
- Download datasheet (902Kb)
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 1.83: Typical transmit/receive timings in clock synchronous serial I/O mode Polarity select
Example of receive timing (when external clock is selected)
function
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
RTSi
CLKi
RxDi
Receive complete
flag (Rl)
Receive interrupt
request bit (IR)
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CTSi
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
Transmit interrupt
request bit (IR)
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
The above timing applies to the following settings:
f
EXT
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
: frequency of external clock
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“H”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
Transferred from UARTi receive register
to UARTi receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
Data is set in UARTi transmit buffer register
D
Transferred from UARTi transmit buffer register to UARTi transmit register
Dummy data is set in UARTi transmit buffer register
0
D
D
0
1
D
D
1
2
T
D
D
CLK
2
3
D
D
3
4
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / f
Receive data is taken in
D
D
Tc
4
5
EXT
D
D
5
Cleared to “0” when interrupt request is accepted, or cleared by software
6
1-94
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
6
7
Read out from UARTi receive buffer register
D
7
Stopped pulsing because CTS = “H”
D
0
D
D
0
Tc = TCLK = 2(n + 1) / fi
1
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit
• Receive enable bit
• Dummy data write to UARTi transmit buffer register
D
D
1
2
fi: frequency of BRGi count source (f
n: value set to BRGi
D
D
2
3
D
D
3
4
D
D
4
5
D
5
D
6
“1”
“1”
D
7
Mitsubishi microcomputers
Stopped pulsing because transfer enable bit = “0”
M30240 Group
D
0
1
D
, f
1
8
, f
D
32
2
)
D
3
D
4
D
5
D
6
D
7
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