M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 12

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Specifications in this manual are tentative and subject to change
Central Processing Unit (CPU)
2.1.2 Address registers (A0 and A1)
2.1.3 Frame base register (FB)
2.1.4 Program counter (PC)
2.1.5 Interrupt table register (INTB)
2.1.6 Stack pointer (USP/ISP)
2.1.7 Static base register (SB)
2.1.8 Flag register (FLG)
2.1.8.1 Bit 0: Carry flag (C flag)
2.1.8.2 Bit 1: Debug flag (D flag)
2.1.8.3 Bit 2: Zero flag (Z flag)
2.1.8.4 Bit 3: Sign flag (S flag)
2.1.8.5 Bit 4: Register bank select flag (B flag)
2.1.8.6 Bit 5: Overflow flag (O flag)
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1, can
be used as 32-bit data registers (R2R0/R3R1).
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of
data registers. These registers can also be used for address register indirect addressing and address
register relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be execut-
ed.
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vec-
tor table. INTB can be used as separate registers of four high-order bits and 16 low-order bits.
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each con-
figured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.6 shows the flag reg-
ister (FLG). The following explains the function of each flag:
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0”
when the interrupt is acknowledged.
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
This flag chooses a register bank. Register bank 0 is selected when this flag is “0”; register bank 1 is selected
when this flag is “1”.
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
1-12
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M30240 Group