M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 61

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Universal Serial Bus
Figure 1.48: USB Endpoint x OUT CSR
Figure 1.49: USB Endpoint x IN MAXP
2.18.4.17 USB Endpoint x IN MAXP Register
When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data pack-
et), the CPU sets this bit to a “1” and then resets it to a “0” to initialize the respective endpoint’s data toggle.
Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction
to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/
TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event.
• OUTxCSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” when the host sends out a larger data packet than the MAXP size. The
USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear this bit.
• OUTxCSR5 (DATA_ERR):
The USB FCU sets this bit to a “1” to indicate that a CRC error or a bit stuffing error was received in an ISO
packet. The CPU writes a “0” to clear this bit.
• OUTxCSR6 (FLUSH):
The CPU writes a “1” to this to flush the OUT FIFO. When there is one packet in the OUT FIFO, a flush causes
the OUT FIFO to be empty. When there are two packets in the OUT FIFO, a flush causes the older packet to
be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce un-
predictable results.
• OUTxCSR7 (AUTO_CLR):
When the CPU sets this bit to a “1”, the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the
number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see “OUT
(Receive) FIFO” for details).
The USB Endpoint x IN MAXP Register, shown in Figure 1.49, indicates the maximum packet size (MAXP) of
an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also
affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet
mode is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
USB Endpoint x OUT Control and Status Register (Note 3)
b7
USB Endpoint x IN MAXP Register
b7
b6
b5
b6
b4
b5
b3
b4
b2
b3
b1
b2
b0
b1
Note 1: Write "0" only or read
Note 2: Write only - Read "0"
Note 3: Refer to section 5.5 "Programming Notes" for this register
Bit symbol
OUTxCSR0
OUTxCSR1
OUTxCSR2
OUTxCSR3
OUTxCSR4
OUTxCSR5
OUTxCSR6
OUTxCSR7
b0
Symbol
EPiOCS (i = 1-4)
Bit symbol
IMAXP0 to
IMAXP7
Symbol
EPiIMP (i = 1-4)
OUT_PKT_RDY Flag
OVER_RUN Flag
SEND_STALL Bit
ISO Bit
FORCE-STALL Flag
DATA-ERR Flag
FLUSH Bit
AUTO_CLR Bit
Bit name
Maximum packet size
(MAXP) of Endpoint x IN
packet.
1-61
031A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
031B
16,
Bit name
0322
Address
0 : Not ready
1 : Ready
0 : No FIFO overrun
1 : FIFO overrun occured
0 : No action
1 : Stall OUT Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : No action
1 : Stall Endpoint X by the USB FCU
0 : No error
1 : CRC or bit stuffing error received in ISO packet
0 : No action
1 : Flush the FIFO
0 : AUTO-CLR disabled
1 : AUTO-CLR enabled
16,
16,
0323
032A
Address
16,
For endpoints that support smaller
FIFO size, unused bits are not
implemented, (always write "0" to
those bits).
16,
032B
0332
16,
16
0333
Function
16
Function
When reset
00
When reset
16
00
Mitsubishi microcomputers
16
M30240 Group
R
R
Note 1
Note 1
Note 1
Note 1
Note 2
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
W
W