M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 29

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Interrupts
2.14 Interrupts
Table 1.8:
Note: Interrupts used for debugging purposes only
Figure 1.15: Format for specifying interrupt vector addresses
Undefined instruction
Overflow
BRK instruction
Address Match
Single Step (Note)
Watchdog timer
DBC (Note)
NMI
Reset
Interrupt source
Table 1.8 and Table 1.9 show the interrupt sources and vector table addresses. When an interrupt is
received, the program is executed from the address shown by the respective interrupt vector.
The vector table addresses for the interrupts in Table 7 are fixed (interrupt vector addresses). These
interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupts in Table 8 are variable, being determined as relative to the
fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using
the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table
register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT
instruction to specify a software interrupt number, the program can be executed starting at the address
indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed
vector address and variable vector address. When the contents of FFFE4
“FF
variable vector address.
Specify the starting address of the interrupt program in the interrupt vector. Figure 1.15 shows the format
for specifying the address.
16
), the program is executed from the address shown in the BRK instruction interrupt vector in the
Interrupt vectors (fixed interrupt vector addresses)
FFFDC
FFFE0
FFFE4
FFFE8
FFFEC
FFFF0
FFFF4
FFFF8
FFFFC
Address(L) to Address(H)
Vector table addresses
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
16
16
16
16
16
16
16
16
16
to FFFE3
to FFFE7
to FFFEB
to FFF3
to FFFF7
to FFFFB
to FFFFF
to FFFEF
to FFFDF
16
16
16
16
16
16
16
16
16
1-29
MSB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0 0 0 0
0 0 0 0
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Do not use
External interrupt by NMI pin
Low address
Mid address
High address
0 0 0 0
LSB
Remarks
16
Mitsubishi microcomputers
, program execution starts from
16
M30240 Group
through FFFE7
16
are all