M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 43

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Frequency Synthesizer Circuit
Figure 1.27: Frequency Synthesizer Control Register (FSC)
Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR)
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSC0 = “0”), f
active (FSC0 = “1”), a lock status (LS = “1”) indicates that f
LS and FSCO control bits in the FSC Control register are shown in Figure 1.27.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the
frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that
none of the registers be modified once the frequency synthesizer is enabled as it will cause the output
to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer
Clock Control register (FSCCR). See Figure 1.28.
Note: None of the registers must be written to once the frequency synthesizer is enabled and used as
the system clock source (FSCCR register, address 03DB
output of the PLL to freeze. Switch system back to f(X
Frequency Synthesizer Control Register
b7
Frequency Synthesizer Clock Control Register
b7
0 0
b6
b6
b5
b5
0 0 0 0 0
0 0
VCO
b4
b4
b3
b3
b2
is held at either a high or low state. When the frequency synthesizer control bit is
b2
b1
b1
b0
Note 1: Recommended
CHG0
CHG1
b0
Bit symbol
Reserved bit
LS
VCO0
VCO1
FSE
Bit symbol
Symbol
FSC
FSCCR0
Reserved
Symbol
FSCCR
Frequency Synthesizer Enable
VCO Gain Control
LPF Current Control
Frequency Synthesizer
Lock Status
Clock source selection
Bit name
1-43
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit name
IN
Address
03DC
) and disable before modifying PLL registers.
Bit 6
0
0
1
1
0:
1:
Bit 2
0
0
1
1
0 : Disable
1 : Enabled
Must always be set to "0"
16
SYN
16
Address
03DB
, bit ‘0’ set to ‘1’) because it will cause the
Bit 5
0:
1:
0:
1:
Unlocked
Locked
Bit 1
0:
1:
0:
1:
and f
16
Must always be set to "0"
0 : Xin
1 : fsyn
Function
Disabled
Low Current
Intermediate Current (Note 1)
High Current
Lowest Gain (Note 1)
Low Gain
High Gain
Highest Gain
VCO
are the correct frequency. The
Function
Mitsubishi microcomputers
When reset
M30240 Group
When reset
60
00
16
16
R
R
W
W