M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 47

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Universal Serial Bus
2.18.3 USB Endpoint FIFOs
2.18.2.4 USB SOF Interrupt
2.18.3.1 IN (Transmit) FIFOs
The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU
generates a USB SOF Interrupt request when a start-of-frame packet is received.
Register SOFIC contains the USB SOF Interrupt’s request bit and its interrupt priority select bits, which are
used to enable the interrupt and set its software priority level.
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Each endpoint (ex-
cept endpoint 0) can be configured to support either single packet mode (in which only a single data packet
is allowed to reside in the endpoint’s FIFO) or dual packet mode (in which up to two data packets are allowed
to reside in the endpoint’s FIFO). Dual packet mode provides support for back-to-back transmission or back-
to-back reception. The mode is automatically determined by the MAXP value. When MAXP > 1/2 of the end-
point’s FIFO size, single packet mode is set. When MAXP <= 1/2 of the endpoint’s FIFO size, dual packet
mode is set.
In the event of a bad transmission/reception, the USB FCU handles all the FIFO read/write pointer reversal
and data set management tasks required.
Throughout this specification, the terms “IN FIFO” and “OUT FIFO” usually refer to the FIFOs associated with
a specific endpoint.
The CPU/DMA writes data to the endpoint’s IN FIFO location specified by the FIFO write pointer, which auto-
matically increments by “1” after a write. The CPU/DMA should only write data to the IN FIFO when the
IN_PKT_RDY bit of the associated IN CSR is a “0”.
• Endpoint 0 IN FIFO Operation:
The CPU writes a “1” to the IN_PKT_RDY bit of Endpoint 0 CSR after it finishes writing a packet of data to the
IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the
host (i.e., ACK is received from the host) or the SETUP_END bit of the IN CSR is set to a “1”.
• Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = “0” (disabled):
MAXP > 1/2 of the IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit of the associated IN CSR after
the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit
after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers
and is concluded when an ACK is received from the host for non-isochronous transfers).
MAXP <= 1/2 of the IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit of the associated IN CSR
after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY
bit as soon as the IN FIFO is ready to accept another data packet. (The FIFO can hold up to two data packets
at the same time in this configuration for back-to-back transmission.)
• Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = “1” (enabled):
MAXP > 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size)
has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit of the associated
IN CSR to a “1” automatically. The USB FCU clears the IN_PKT_RDY bit after the packet has been success-
fully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is
received from the host for non-isochronous transfers).
MAXP <= 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet
size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a “1”
automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another
data packet. (The FIFO can hold up to two data packets at the same time in this configuration for back-to-back
transmission.)
A software or a hardware flush causes the USB FCU to act as if a packet has been successfully transmitted
out to the host. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there
are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. A flush
also updates the IN FIFO status bits IN_PKT_RDY and TX_NOT_EMPTY of the associated IN CSR.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M30240 Group