M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 11
M30240ECFP
Manufacturer Part Number
M30240ECFP
Description
M30240 Group Specification
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M30240ECFP.pdf
(142 pages)
- Current page: 11 of 142
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Specifications in this manual are tentative and subject to change
Central Processing Unit (CPU)
2.0 Operation of Functional Blocks
2.1 Central Processing Unit (CPU)
Figure 1.5:
2.1.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
R2
R0
R1
R3
A0
A1
FB
The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D
converter, and I/O ports.
The following explains each unit.
The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer
and arithmetic/logic operations.
Note: These registers consist of two register banks.
b15
b15
b15
b15
b15
b15
b15
Central processing unit register
H
H
b8 b7
b8 b7
L
L
b0
b0
b0
b0
b0
b0
b0
Frame base
registers
Data
registers
Address
registers
IPL
1-11
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PC
INTB
b19
b19
USP
SB
ISP
FLG
H
b15
b15
b15
U
b15
I
O
B
L
S
Z
Mitsubishi microcomputers
M30240 Group
D
C
b0
b0
b0
b0
b0
b0
Interrupt table
register
Interrupt stack
pointer
Static base
register
Program counter
User stack pointer
Flag register
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