M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 24

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Specifications in this manual are tentative and subject to change
Clock Control
2.8 Clock Control
Figure 1.12: Clock-generating circuit
2.8.1 Main clock
2.8.2 Internal clock
Figure 1.12 shows the block diagram of the clock-generating circuit.
The following paragraphs describe the clocks generated by the clock-generating circuit.
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the internal clock
0006
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the f(Xout)
pin can be reduced using the f(Xin)-f(Xout) drive capacity select bit (bit 5 at address 0007
the drive capacity of the f(Xout) pin reduces the power dissipation. This bit defaults to “1” when shifting
to stop mode and after a reset.
The internal clock
viding the main clock by 2, 4, 8, or 16. The internal clock
after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 0006
16
Software reset
). Stopping the clock reduces the power dissipation.
RESET
Interrupt request
level judgment
output
NMI
is the clock that drives the CPU, and is either the main clock or is derived by di-
WAIT instruction
CM0i :
CM1i :
FSCCRi: Bit i at address 03DB
CM10 “1”
Write signal
. The clock can be stopped using the main clock stop bit (bit 5 at address
Bit i at address 0006
Bit i at address 0007
S
R
S
R
Q
Q
16
16
16
X
IN
Main clock
1-24
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FSCCR0=1
FSCCR0=0
X
a
OUT
CM02
Synthesizer
Frequency
Circuit
CM06=0
CM17,CM16=00
1/2
is derived by dividing the main clock by 8
CM06=0
CM17,CM16=01
fsyn
1/2
CM06=0
CM17,CM16=10
a
1/2
Divider
b
Mitsubishi microcomputers
c
M30240 Group
b
CM06=1
16
d
f
f
usb (48MHz)
f
AD
) is set to “1”.
32
f
f
1
8
1/2
Details of divider
CM06=0
CM17,CM16=11
f
f
f
1
8
32
SIO2
SIO2
1/2
SIO2
16
Internal clock
). Reducing
c
d