M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet - Page 13

• Manufacturer Part Number: M30240ECFP
• Description: M30240 Group Specification
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Central Processing Unit (CPU)
Figure 1.6:
2.1.8.7 Bit 6: Interrupt enable flag (I flag)
2.1.8.8 Bit 7: Stack pointer select flag (U flag)
2.1.8.9 Bits 8 to 11: Reserved area
2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL)
2.1.8.11 Bit 15: Reserved area
b15
The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual
for details.
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
Interrupt stack pointer (ISP) is selected when this flag is “0”; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software inter-
rupts 0 to 31 is executed.
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor
interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is en-
abled.
IPL
Flag register (FLG)
U
I
O
B
1-13
S
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Z
D
C
b0
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
Mitsubishi microcomputers
M30240 Group