MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet
MT41J64M16JT-15E AIT:G
Related parts for MT41J64M16JT-15E AIT:G
MT41J64M16JT-15E AIT:G Summary of contents
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... Backward compatible to 1066 (-187E). Notes: 2. Backward compatible to 1333 (-15E). PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x8, x16 Automotive DDR3 SDRAM 1 Options • Configuration – 128 Meg x 8 – 64 Meg x 16 • ...
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... FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – ...
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... DLL Disable Mode ..................................................................................................................................... 109 Input Clock Frequency Change ...................................................................................................................... 113 Write Leveling ............................................................................................................................................... 115 PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... Timing Parameters .................................................................................................................................... 187 ODT Off During READs .............................................................................................................................. 190 Asynchronous ODT Mode .............................................................................................................................. 192 PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 196 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 198 PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... IH (Command and Address – Clock) ............................................................ VAC for DS (DQ – Strobe) .......................................................................... (DQ – Strobe) ....................................................................................... 99 t MRD) ......................................................................................... 122 t MOD) .................................................................................. 123 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Features ...
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... Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM t RCD (MIN) ............................................................................. 143 t DQSQ and Data Valid Window .................................................................... 152 and HZ ............................................................................................... 154 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Features ...
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... Figure 117: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 199 PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... DVAC) for CK - CK# and DQS - DQS# ............................................... 43 Characteristics 1.5V ................................................................ 55 DD DDQ Characteristics 1.575V ............................................................. 55 DD DDQ Characteristics 1.425V ............................................................. 56 DD DDQ 9 .................................................................... 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Features ...
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... IH – AC125/DC100-Based ............................................................................ 89 t VAC Above V for Valid Transition ...................................................... 90 IH(AC – AC175/DC100-Based ......................................................................... – AC150/DC100-Based ......................................................................... – AC135/DC100-Based ......................................................................... 97 (Below V ) for Valid Transition ................................................ 97 IH(AC) IL(AC) ............................................................................................................. 182 ............................................................................................................. 183 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Features ...
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... PRE, PREA SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. CKE L Self refresh Automatic ...
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... ODT resistance and the input/output impedance must be derated when T 0°C or > +95°C. PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM Functional Description 12 Micron Technology, Inc. reserves the right to change products or specifications without notice < C ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM via 1k * resistor. DD via 1k * resistor Micron Technology, Inc. reserves the right to change products or specifications without notice. Functional Description via 1k resistors,* or float REF ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... Data TT,nom and interface Data input sw1 logic CK, CK# Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. /2 DDQ R TT(WR) sw2 ( DQ8 TDQS# DQ[7:0] /2 DDQ ...
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... TT,nom and interface Data input sw1 logic Column 2 CK, CK# (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. R TT(WR) sw2 ( 16) DQ[15:0] R TT(WR) sw2 LDQS, LDQS# UDQS, UDQS# (1 ...
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... DD SS SSQ DQ7 DQ5 V DDQ CK# CKE V DD A10/ REFCA SS A12/BC# BA1 A11 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... DD SS SSQ DQ7 DQ5 V DDQ CK# V CKE DD A10/ REFCA SS A12/BC# BA1 A11 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... RESET# assertion and de-assertion are asynchronous. DDQ 18 Ball Assignments and Descriptions . REFCA . REFCA . DM has an optional use as TDQS on the x8 REFCA . The RESET# input SS Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0.8 × V and DD ...
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... No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4]. 19 Ball Assignments and Descriptions must be REFCA must be maintained at all times (excluding self . SSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... DC LOW 0.2 × RESET# assertion and de-assertion are asynchronous. DDQ 20 Ball Assignments and Descriptions . REFCA . REFCA . REFDQ . REFCA . The RESET# input SS Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0.8 × V and DD ...
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... No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 21 Ball Assignments and Descriptions . REFCA must be maintained at all times (excluding self . SSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. . REFDQ must be ...
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... Automotive DDR3 SDRAM 0.8 ±0.1 8 ±0.1 Ball 11.5 ±0 6.4 CTR 22 Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... Ball ±0. 0.8 TYP 6.4 CTR 8 ±0.15 23 Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... T C –40 to +105 ° 6.4 °C/W JC 6.4 is measured in the center of the package. C Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Notes dur- C ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. -107 13-13-13 Unit 1.071 ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – 0 – 0 – 0 – 0 – 0 00000000 0 – 0 – 0 – 0 – 0 – ...
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... CK (MIN n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Midlevel Enabled Enabled, off 8 None All n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. I Active DD3P Current n/a LOW Toggling t CK (MIN n/a n/a n/a n/a n/a n/a n/a HIGH LOW ...
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... F . DD3N Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 00000000 0 – 0 – 0 – 0 00110011 0 – 0 – 0 – ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 00000000 0 – 0 – 0 – 0 00110011 0 – 0 – 0 – ...
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... Specifications and Conditions Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – 0 – 0 – 0 – 0 – ...
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... Midlevel Midlevel Midlevel Midlevel Midlevel Enabled Enabled, midlevel n/a n/a n/a Enabled (extended) Disabled t RFC. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved Reset DD8 Midlevel Midlevel n/a n/a n/a n/a n/a n/a n/a n/a Midlevel Midlevel Midlevel Midlevel Midlevel ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – 0 00000000 0 – 0 – 0 00110011 0 – 0 – 0 – 0 – 0 00110011 0 – ...
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... Repeat sub-loop 11, use BA[2: Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed 35 Specifications and Conditions Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0 – ...
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... DD3P DD4R must be derated by 7 DD2NT DD2Q DD3N DD3P DD4R Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Specifications Units Notes ...
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... DDQ and to track variations in the DC DD REFCA REFCA and to track variations in the DC DD REFDQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes μA μA 4 ...
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... All REF REFCA REF t DS) are referenced IL(AC) t DH) are referenced IL(DC) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit – mV – – ...
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... V levels with ringback IL IH 1.90V 1.50V 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V 0.0V –0.40V 39 Micron Technology, Inc. reserves the right to change products or specifications without notice 0.4V narrow DDQ pulse width V DDQ V IH(AC) V IH(DC noise REF error REF V ...
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... Vns 0.4 Vns 0.33 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.19 Vns 0.15 Vns 0.13 Vns 0.19 Vns 0.15 Vns 0.13 Vns Overshoot area Time (ns) Undershoot area Time (ns) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 0.4V 0.4V 0.28 Vns 0.28 Vns 0.4V 0.4V 0.11 Vns 0.11 Vns ...
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... REFDQ(DC) of the transmitting device indicates the voltage at which DD IX(AC least V SEL SEH DD Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes ...
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... V SEL,max SSQ 42 Electrical Specifications – DC and DQS V SEL Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved DDQ CK#, DQS / DDQ V IX CK, DQS ...
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... DVAC (ps IH,diff(AC) IL,diff(AC) 350mV Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. | 300mV 175 170 167 163 162 161 159 155 150 150 ...
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... IH(AC)min IH(AC)min IL(AC)max REF REF REF V V REF IH(DC)min TRSH Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved and DS and DH REF TRS se IL(AC)max TFS se ...
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... Figure 16: Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM Electrical Specifications – DC and AC TFS se TFH se 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. TRS se V IH(AC)min V IH(DC)min V or REFDQ V REFCA ...
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... The nominal slew rate for a IH,diff,min and V IH,diff,min IL,diff,max To Calculation V V IH,diff,min IH,diff,min V V IL,diff,max IH,diff,min TR diff Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved IL,diff,max TR diff - V IL,diff,max TF diff V IH,diff,min 0 V IL,diff,max ...
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... Refer to ODT Sensitivity DDQ DD SSQ SS to pin under test and measure current IH(AC and R TT120(PU240) TT60(PU120) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes IL(AC) ...
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... DDQ 0.9 IL(AC) IH(AC) 0.2 × V 0.6 DDQ 0.5 × V 0.9 DDQ 0.8 × V 0.9 DDQ 0.2 × V 0.9 DDQ 0.5 × V 0.9 DDQ 0.8 × V 0.6 DDQ 0.9 IL(AC) IH(AC) 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. ODT Characteristics Nom Max Unit 1.0 1.1 RZQ/1 1.0 1.1 RZQ/1 1.0 1.4 RZQ/1 1.0 1.4 RZQ/1 1.0 1.1 RZQ/1 1.0 1.1 RZQ/1 1.0 1.6 RZQ/2 1.0 1.1 RZQ/2 1.0 1.1 RZQ/2 1 ...
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... calibration) and DDQ DD Max 1.5 0. calibration) and DDQ DD Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 Unit . DDQ Unit %/°C %/mV ...
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... DDQ DD SSQ SS Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Figure V SW2 100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 300mV ...
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... ODT first registered low CK CK# t AONPD T SW2 T SW1 V V SW2 SW2 V SW1 End point: Extrapolated point at V SSQ 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. ODT Characteristics V /2 DDQ t AOF End point: Extrapolated point at V RTT,nom V RTT,nom T SW1 T SW1 V SW1 V ...
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... SW21 T V SW11 SW2 RTT,nom V SW1 V RTT(WR) 52 ODT Characteristics t ADC V RTT,nom T SW22 T SW12 End point: Extrapolated point at V RTT(WR) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved DDQ V SSQ ...
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... ON(PD Output Driver Impedance with respectively) and R are defined as fol- ON(PU) ON(PD) is turned off ON(PD) is turned off V DDQ DQ V OUT V SSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... ON34 Nom Max 1.0 1.1 1.0 1.1 1.0 1.4 1.0 1.4 1.0 1.1 1.0 1.1 n DDQ : DDQ ). C Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved RZQ/7 (with Unit Notes RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ SSQ SS ). Meas- PUPD ...
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... Nom Max 20.4 34.3 38.1 30.5 34.3 38.1 30.5 34.3 48.5 30.5 34.3 48.5 30.5 34.3 38.1 20.4 34.3 38.1 = 1.5V Nom Min 8.8 7.9 21.9 19.7 35.0 24.8 35.0 24.8 21.9 19.7 8.8 7.9 = 1.575V Nom Min 9.2 8.3 23 20.7 36 20.7 9.2 8.3 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. and R are ON34(PU) Unit Unit Unit Unit ...
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... dVH × and DDQ(@CALIBRATION) DD DDQ Max 1.5 0.13 1.5 0.13 1.5 0.13 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Unit RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 Unit %/° ...
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... dTH × dVH × and DDQ(@CALIBRATION) DD DDQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ ...
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... Change Min dR dTM dVM dTL dVL dTH dVH Micron Technology, Inc. reserves the right to change products or specifications without notice. Output Driver Impedance Max Unit 1.5 %/°C 0.15 %/mV 1.5 %/°C 0.15 %/mV 1.5 %/°C 0.15 %/mV ‹ 2010 Micron Technology, Inc. All rights reserved. ...
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... DDQ V - 0.1 × DDQ –10 10 PUPD Output /2) via 25 resistor TT DDQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes μ ...
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... V DDQ – /2) via 25 resistor TT DDQ MAX output V OH(AC) V OL(AC) MIN output Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes μ ...
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... DQ TT DQS DQS# Timing reference point ZQ RZQ = 240 DDQ V SS Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. MAX output OX(AC)max V OX(AC)min V OL MIN output ...
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... Output Characteristics and Operating Conditions and V OL(AC) Edge From DQ Rising V OL(AC) Falling V OH(AC for single-ended signals. OH(AC) Measured To Calculation V V OH(AC) OH(AC OL(AC) OH(AC OH(AC OL(AC) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved OL(AC OL(AC ...
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... Automotive DDR3 SDRAM Output Characteristics and Operating Conditions and V OL(AC) OH(AC) Measured Edge From Rising V OL,diff(AC) Falling V OH,diff(AC) TF diff 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. for differential signals. To Calculation OH,diff(AC) OH,diff(AC) OL,diff(AC) TR diff OL,diff(AC) OH,diff(AC) ...
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... Reserved <2.5 Reserved Reserved Reserved <2.5 1.875 <2 requirements. When making a selection of Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes ...
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... Reserved Reserved Reserved <1.875 1.5 <1.875 requirements. When making a selection of Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes ...
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... Reserved Reserved 1.5 <1.875 Reserved Reserved 1.25 <1 10 requirements. When making a selection of Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes ...
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... Reserved Reserved Reserved Reserved 1.071 <1. 10, 11 requirements. When making a selection of Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Unit Notes ...
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Electrical Characteristics and AC Operating Conditions Table 51: Electrical Characteristics and AC Operating Conditions Notes 1–8 apply to the entire table Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C to 95°C C ...
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Table 51: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data setup time to Base (specification) DQS, DQS ...
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Table 51: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# Low-Z time ( DQS, DQS# High-Z time (RL + BL/2) DQS, DQS# differential READ preamble DQS, DQS# differential READ ...
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Table 51: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter MODE REGISTER SET command cycle time MODE REGISTER SET command update delay MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose ...
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Table 51: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Valid clocks after self refresh entry or power- down entry Valid clocks before self refresh exit, power-down exit, or reset exit CKE MIN ...
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Table 51: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter DLL on, any valid command, or DLL off to commands not requiring locked DLL Precharge power-down with DLL off to commands requiring a ...
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... Strobe or DQS 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. 9. When operating in DLL disable mode, Micron does not warrant compliance with normal 10. The clock’s 11. Spread spectrum is not included in the jitter specification values. However, the input 12. The clock’ ...
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... RP = 5ns, the device will t RAS (MIN) has been satisfied. is less than or equal to 85°C. This equates to an aver- C Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t DQSCK (MAX), ...
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... ADC (MAX) and t t ERR10per (MAX) and JITdty (MAX). . REF(DC) t RFC (MIN), an AUTO REFRESH command should Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t XPDLL (MIN) t JITdty when t AOF (MAX) are ...
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Electrical Characteristics and AC Operating Conditions Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1–8 apply to the entire table Parameter Clock period average: DLL disable T = 0°C to 85°C C mode T = >85°C ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Cumulative error across 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE 1KB page size minimum command period 2KB page size Four ACTIVATE 1KB page ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter RESET# LOW to power supplies stable RESET# LOW to I/O and R High-Z TT REFRESH-to-ACTIVATE or REFRESH command period Maximum ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Power-down exit period: ODT either synchronous or asynchronous ACTIVATE command to power-down entry PRECHARGE/PRECHARGE ALL command to power-down entry REFRESH ...
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Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter ODT HIGH time without WRITE command or with WRITE command and BC4 R -to-R change skew TT,nom TT(WR) R -to-R ...
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... Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. 9. When operating in DLL disable mode, Micron does not warrant compliance with normal 10. The clock’s 11. Spread spectrum is not included in the jitter specification values. However, the input 12. The clock’ ...
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... RP = 5ns, the device will t RAS (MIN) has been satisfied. is less than or equal to 85°C. This equates to an aver- C Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t DQSCK (MAX), ...
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... ADC (MAX) and t t ERR10per (MAX) and JITdty (MAX). . REF(DC) t RFC (MIN), an AUTO REFRESH command should Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t XPDLL (MIN) t JITdty when t AOF (MAX) are ...
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... REF(DC) DDR3-1866 Unit – ps – ps – – 150 ps 100 ps Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t IS. For a valid for some time and REF(DC) and IH(DC)min Reference V /V IH(AC) IL(AC) V ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 1.0 V/ 128 100 ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 1.0 V/ 108 100 n/a ...
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... VAC at 135mV (ps) VAC at 125mV (ps) 175 160 150 140 130 120 110 105 n/a n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 200 190 180 170 160 150 n/a n/a n/a n/a ...
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... VAC Setup slew rate REF(DC) IL(AC)max = rising signal VAC Nominal slew rate REF region IH(AC)min REF(DC Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 92
... REF(DC) IL(DC)max = Nominal slew rate REF region Hold slew rate IH(DC)min REF(DC) = falling signal TF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 93
... VAC line Tangent line REF region TR Tangent line ( IH(DC)min REF(DC Tangent line ( REF(DC) IL(AC)max TF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved ...
Page 94
... Tangent line (V Hold slew rate falling signal = Nominal line Tangen t line Nominal line REF(DC) IL(DC)max IH(DC)min REF(DC) TF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 95
... REF(DC) region is used for derating val- REF(DC) DDR3-1866 Unit – ps – Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. REF(DC) IH(DC)min Reference V /V IH(AC) IL(AC IH(AC) IL(AC) V ...
Page 96
... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 1.0 V/ – –26 –22 –10 1 ...
Page 97
... Valid Transition t VAC at 135mV (ps) Min Min 175 187 170 165 167 121 163 162 161 159 155 150 150 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. 1.0 V/ n/a n/a n/a n/a n/a ...
Page 98
... REF(DC) IL(AC)max = rising signal TF 98 Data Setup, Hold, and Derating VAC Nominal slew rate REF region IH(AC)min REF(DC Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 99
... DH REF Nominal slew rate Hold slew rate REF(DC) IL(DC)max = falling signal TR 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. Data Setup, Hold, and Derating Nominal slew rate REF region IL(DC)min REF(DC) ...
Page 100
... Data Setup, Hold, and Derating VAC Nominal line Tangent line REF region TR Tangent line ( IH(AC)min REF(DC Tangent line ( REF(DC) IL(AC)max TF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved ...
Page 101
... Data Setup, Hold, and Derating Nominal line Tangent line Nominal line REF(DC) IL(DC)max IH(DC)min REF(DC) TF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 102
... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. A[11, 9:0] Notes ...
Page 103
... MR0. ted commands. A NOP will not terminate an operation that is executing. tion) or ZQoper (ZQCL command after initialization). 103 Commands – Truth Tables Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 104
... Active power-down entry Power-down entry Power-down entry Power-down entry Precharge power-down entry Precharge power-down entry Self refresh CKE (MIN) + IH. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Notes 6 ...
Page 105
... ZQCS. A ZQCS command can effectively correct a minimum of 0.5% R impedance error within 64 clock cycles, assuming the maximum sensitivities TT 105 and ODT values ZQinit or ZQoper to perform t ZQoper to be satis- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands ON ...
Page 106
... RFU RFU RFU RFU RFU H Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands A[11, A10 9: A[11, A10 9:0] L ...
Page 107
... REFRESH commands is allowed. PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 85°C or 3.9μs maximum when T C 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. Commands t RP) 95°C). The REFRESH period C t RFC (MIN) later. ‹ ...
Page 108
... NOP RFC (MIN) RFC Indicates break in time scale /2 while in self refresh mode under DDQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands Tb2 5 5 ACT Don’t Care ...
Page 109
... DQSCK starts cy- MR2[10 while in the DLL disable TT(WR) are High-Z), set MR1[ disable the TT(WR) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands t DQSCK [AVG] MAX ...
Page 110
... LOW or HIGH. TT(WR) are High-Z), enter self refresh mode. t MRD, then set MR0[8] t DLLK after DLL RESET must Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands Tf0 Valid 1 1 Valid ...
Page 111
... DQSQ, QH). Special attention is needed to t DQSCK starts from the rising clock edge DQSCK starts cycles Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands Tg0 Th0 Valid DLLK ...
Page 112
... Transitioning Data Min Max 1 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Commands T9 T10 NOP NOP ...
Page 113
... Input Clock Frequency Change t CKSRE must occur after CKE goes LOW t CK [AVG] MAX). During the input t CKSRX before pre- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved has ...
Page 114
... DLL RESET t XP Exit precharge Indicates break in time scale will remain in the off state. The ODT signal can TT Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Te0 Te1 ...
Page 115
... 115 Write Leveling t DSH specifications in systems that use Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved Don’t Care ...
Page 116
... R values are allowed. This simulates a normal write state to DQS. TT,nom 116 Write Leveling DRAM State TT TT Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Case Notes ...
Page 117
... WPRE) have been satisfied, the memory t DQSL (MIN) and t DQSH (MAX) specifications are not applicable t WLO. The remaining DQ that always t WLOE after the first Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t DQSH t WLO is sat- ...
Page 118
... NOP DQSL DQSH t t WLO WLO t WLO t WLO Undefined Driving Mode t DQSH (MIN) and Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. NOP NOP Don’t Care t DQSL ...
Page 119
... NOP MRS NOP Valid t MRD Valid MR1 t MOD Undefined Driving Mode Transitioning Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t MOD t MRD Te0 Te1 NOP Valid Valid Don’t Care ...
Page 120
... XPR has been satisfied, MRS commands and R values for the process voltage ZQinit must be satisfied. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Initialization is also High-Z). and within , and V ...
Page 121
... MR0 with MR3 MR1 with ZQ calibration DLL reset DLL enable t DLLK Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Initialization Td0 Valid Valid Valid Valid Valid Valid ...
Page 122
... MRD Indicates break in time scale t MRSPDEN (MIN) (see Pow- t MOD in order to update the requested features, Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Ta2 2 MRS Valid Don’t Care t RP (MIN) ...
Page 123
... NOP NOP t MOD Updating setting Indicates break in time scale t MRSPDEN (MIN), at which Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Ta2 non MRS Valid Valid New setting Don’t Care ...
Page 124
... A12 Fixed BC4 (chop Reserved CAS Latency M3 READ Burst Type Reserved 0 Sequential (nibble Interleaved Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 125
... Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Notes ...
Page 126
... NOP NOP NOP NOP Transitioning Data t DSDQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved NOP NOP DI n Don’t Care ...
Page 127
... Additive Latency (AL Disabled ( Reserved 1 1 values are available TT,nom Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t MOD before ini- write values TT,nom ...
Page 128
... The OUTPUT DATA STROBE function of RDQS is not provided TT does not apply to TDQS and TDQS#. The TDQS and DM functions ON 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. Mode Register 1 (MR1) t DQSS margining (write ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 129
... TT values and calculations (see On-Die Termi- is turned on (ODTL on RCD (MIN). The only restriction Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved temporarily re- targeted due to t RCD t RCD (MIN ...
Page 130
... Automotive DDR3 SDRAM T2 T6 NOP NOP These functions are controlled via the bits shown in Figure 52. The MR2 is 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. Mode Register 2 (MR2) T11 T12 T13 NOP NOP NOP DO DO ...
Page 131
... CWL = Indicates break Transitioning Data in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Address bus Mode register 2 (MR2) T14 NOP Don’t Care ...
Page 132
... MR2[10, 9]. Dynamic ODT is enabled TT(WR) ) enabled, the DRAM switches from normal ODT (R TT(WR) ) when beginning a WRITE burst and subsequently switches TT(WR) 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. Mode Register 2 (MR2) ) TT,nom ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 133
... MPR Enable M1 M0 MPR READ Function Predefined pattern Dataflow from MPR 0 1 Reserved 1 0 Reserved 1 1 Reserved Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. is disabled, the ) is disabled, dy- ...
Page 134
... All subsequent WRITEs go to the DRAM memory array Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 134 Mode Register 3 (MR3) Function 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 135
... Predefined pattern Burst order Predefined pattern Burst order Predefined pattern n/a n/a n/a n/a n/a n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 136
... Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM Burst Read Length A[2:0] RFU n/a n/a n/a ted MPR agent. 136 Mode Register 3 (MR3) Burst Order and Data Pattern n/a n/a n/a n/a n/a n/a Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 137
Figure 56: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 CK# CK Command PREA MRS 1 NOP READ MOD Bank address 3 Valid A[1: ...
Page 138
Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Tc0 CK# CK Command PREA MRS 1 1 READ READ CCD RP MOD Bank address 3 Valid Valid A[1: ...
Page 139
Figure 58: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Tc0 CK# CK Command PREA MRS 1 1 READ READ CCD MOD Bank address 3 Valid Valid A[1: ...
Page 140
Figure 59: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Tc0 CK Command PREA MRS READ READ MOD CCD Bank address 3 Valid Valid A[1: ...
Page 141
... MRD before initiating a subsequent operation such MOD. Both 141 t MPRR has been satisfied, issue MRS MRD and MOD parameters are shown in Fig- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t MRD ...
Page 142
... Tc0 Tc1 ZQCS NOP NOP NOP High-Z t ZQCS Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved SSQ Tc2 Valid Valid Valid Valid Valid Activ- ities ...
Page 143
... CCD (MIN). t FAW (MIN) param T10 NOP NOP NOP t RCD Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t RCD t RC. T11 RD/WR Col Bank y Don’t Care ...
Page 144
... T10 T11 T19 NOP ACT NOP NOP Row Bank d Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. T20 ACT Row Bank e Bank y Bank y Don’t Care ...
Page 145
... NOP NOP Indicates break Transitioning Data in time scale t RPRE). The LOW state t DQSCK (DQS transition skew Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. T12 NOP Don’t Care t DQSQ ...
Page 146
... RP is met. The PRE- t RAS lockout feature (see t RAS (MIN) is satisfied RTP + RP)*, where * means rounded up to the next Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t RTP starts AL t RTP (MIN ...
Page 147
Figure 64: Consecutive READ Bursts (BL8 CK READ NOP NOP NOP Command t CCD Bank, 2 Address Col n DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 148
Figure 66: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS Notes ...
Page 149
Figure 68: READ (BC4) to WRITE (BC4) OTF CK READ NOP NOP NOP Command t t READ-to-WRITE command delay = RL + CCD Bank, 2 Address Col n DQS, ...
Page 150
Figure 70: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 71: READ to PRECHARGE ( ...
Page 151
... RPRE. This is known as the READ preamble. t RPST, is one half clock from the last DQS, DQS# transition. Dur- t RPST. 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation t QSL. Prior to the READ ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 152
Figure 73: Data Output Timing – DQSQ and Data Valid Window READ NOP Command Bank, 2 Address Col n DQS, DQS (last data valid (first data no longer valid) All ...
Page 153
... HZDQS (MIN) t RPST Bit 5 Bit 6 Bit DQSCK (MAX) DQSCK (MAX) t QSL Bit 4 Bit 5 Bit 6 Bit 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t LZDQ. Fig- t HZDQ HZDQS (MAX) t RPST ...
Page 154
... HZDQS (MAX) are not tied to DQSCK (MAX) (late t RPRE (MIN). The mini- t RPST (MIN RPRE ends Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t LZDQ t DQSCK t DQSCK ...
Page 155
... Automotive DDR3 SDRAM CK CK# DQS RPST begins 155 READ Operation RPST RPST ends Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved ...
Page 156
... WTR and WR starting time may vary, depending on the mode register settings 156 WRITE Operation t DQSS (MIN) and Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t DQSS t CCD clocks t WTR ...
Page 157
... Automotive DDR3 SDRAM T1 t WPRE begins t WPRE WPRE specification WPST begins 157 WRITE Operation WPRE ends V TT WPST WPST ends Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 158
... DSS DSS Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. T9 T10 NOP NOP WPST DQSL t DSS t WPST t DQSL t DSS ...
Page 159
Figure 81: Consecutive WRITE (BL8) to WRITE (BL8 CK WRITE NOP NOP NOP Command t CCD 2 Valid Address DQS, DQS NOP commands are shown for ease of ...
Page 160
Figure 83: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...
Page 161
Figure 85: WRITE to READ (BC4 Mode Register Setting CK WRITE NOP NOP Command Valid 3 Address DQS, DQS NOP commands are shown for ease of illustration; other commands ...
Page 162
Figure 86: WRITE (BC4 OTF) to READ (BC4 OTF CK WRITE NOP NOP NOP Command 3 Valid Address DQS, DQS NOP commands are shown for ease of illustration; ...
Page 163
... NOP Indicates break Transitioning Data in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. T12 Ta0 Ta1 NOP NOP PRE Valid t WR Don’t Care ...
Page 164
... Indicates break Transitioning Data in time scale t WPST. t DQSH and Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved NOP PRE Valid Don’t Care t WR speci- t DQSS ...
Page 165
... Automotive DDR3 SDRAM WPRE DQSH DQSL 165 WRITE Operation Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t WPST Don’t Care ...
Page 166
... REFDQ may float or not REFDQ satisfied and no t CKSRX are not required. However, if the Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. is valid. REFDQ t CKESR t CKSRE ...
Page 167
... RP must be met, and no data bursts can and XSDLL timings start at the first rising t t ISXR at Tc1. CKSRX timing is also measured so that Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Te0 Tf0 Valid Valid Valid 6 7 ...
Page 168
... Range for Self Refresh Mode Normal (0°C to 85°C) Normal and extended (0°C to 95°C) Normal and extended (0°C to 95°C) 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. ) range above 85°C or self C during self refresh: ...
Page 169
... Figure 98 (page 174) t Greater 24ns Figure 102 (page 176) t MOD Figure 101 (page 176) t CPDED has been satis- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Figure t ANPD + ...
Page 170
... Off Slow XPDLL to commands that require the DLL to be locked (READ, RDAP, or ODT on any other valid command 170 Micron Technology, Inc. reserves the right to change products or specifications without notice. Power-Down Mode t CKE has been t XP must be satisfied t XPDLL must be satisfied before the Relevant Parameters ‹ ...
Page 171
... Power-Down Mode Ta1 Ta2 Ta3 NOP NOP NOP CKE (MIN mode Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Ta4 Valid Valid Don’t Care ...
Page 172
... NOP Valid t CKE (MIN XPDLL mode Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Ta1 Valid Don’t Care Tb 2 Valid Don’t Care ...
Page 173
... WRPDEN t CK earlier if BC4MRS. 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. Power-Down Mode Ta7 Ta8 Ta9 Ta10 NOP NOP CPDED t PD Power-down or self refresh entry Indicates break ...
Page 174
... CKE (MIN (MIN RFC (MIN) Indicates break in time scale t RFC is satisfied. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Tb2 Tb3 Tb4 NOP t PD Don’t Care t CK rounded up to ...
Page 175
... ACTPDEN NOP NOP t CPDED t IS PREPDEN 175 Power-Down Mode Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. T7 Don’t Care T7 Don’t Care ...
Page 176
... NOP XPDLL mode Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Ta4 Don’t Care Tb0 NOP Enter power-down mode Don’t Care ...
Page 177
... DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN 1Gb: x8, x16 Automotive DDR3 SDRAM 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. RESET Operation ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 178
... MR0 with MR1 with ZQCAL DLL RESET t ZQinit t DLLK Indicates break in time scale Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Td0 Valid Valid Valid Valid Valid Valid Normal operation ...
Page 179
... TT(EFF) 179 On-Die Termination (ODT) DQ, DQS, DQS#, DM, TDQS, TDQS# , may be different from R targeted due to TT values and calculations, see ODT Charac- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved ...
Page 180
... CK LOW t ODT registered 6 CK LOW R See Table 51 (page 68) TT(ON 0.5 CK ± 0.2 TT(OFF) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Notes used dur- Unit ...
Page 181
... Drive R DQs t MOD + 1CK DQS, DQS# DQs must be disabled. The dy- TT(WR) and R . TT(WR) Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Dynamic ODT ) to dy- TT,nom Final State TT,nom value TT,nom No R TT,nom ...
Page 182
... Mode Restriction TT,nom TT,nom Off 60 Self refresh 120 40 20 Self refresh, write 30 Reserved Reserved Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Dynamic ODT TT,nom . TT,nom Unit ...
Page 183
... Automotive DDR3 SDRAM TT(WR) R (RZQ) TT(WR) Dynamic ODT off: WRITE does not affect R RZQ/4 RZQ/2 Reserved 183 Micron Technology, Inc. reserves the right to change products or specifications without notice. Dynamic ODT R (Ohm) TT(WR) TT,nom 60 120 Reserved ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 184
Figure 105: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 NOP Address Valid ODTH4 ODT ODTLon t AON (MIN AON (MAX) ...
Page 185
Figure 107: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTLcnw Address Valid ODTLon ODT R TT DQS, DQS Via MRS or OTF; ...
Page 186
... Transitioning can be either enabled or disabled. If disabled, TT,nom Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Dynamic ODT T10 T11 NOP NOP t AOF (MIN) t AOF (MAX) Don’ ...
Page 187
... AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured 187 Synchronous ODT Mode t AON and t turn-on time ( AON [MIN]) is the TT turn-off time ( TT Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. t AOF around t AOF [MIN]) is turn TT ...
Page 188
Table 84: Synchronous ODT Parameters Symbol Description ODTLon ODT synchronous turn-on delay ODTLoff ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ODT turn-on ...
Page 189
Figure 111: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTLon = Notes: TT,nom 2. ODT must be held ...
Page 190
... Automotive DDR3 SDRAM enabled). R TT,nom TT(WR) TT 190 Synchronous ODT Mode must be disabled TT may not be enabled until the end of the post- Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. ...
Page 191
Figure 112: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTLoff = CWL + ODT DQS, DQS# DQ Note: 1. ODT must be disabled ...
Page 192
... Asynchronous ODT Mode t t AONPD and AOFPD replace ODTLon/ turn-off time ( TT t AOFPD (MIN) and Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved AON turn AONPD t AOFPD ...
Page 193
Figure 113: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Note ignored. Table 85: Asynchronous ODT Timing Parameters for All ...
Page 194
... ANPD AON (MIN) and AONPD (MAX) > ODTLon × 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. Asynchronous ODT Mode t RFC after the REFRESH command, rath- change as early as the lesser TT t AOFPD (MIN) and ODTLoff × ...
Page 195
Table 86: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Power-down entry transition period (power-down entry) Power-down exit transition period (power-down exit) ODT to R turn-on delay TT (ODTLon = ODT to R ...
Page 196
... This is be ANPD. t AOFPD (MIN) < ODTL AOF (MAX) > AOFPD (MAX). Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Down Exit) t CK. The t AONPD ...
Page 197
Figure 115: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit Ta0 Ta1 CK# CK CKE COMMAND NOP t ANPD ODT A asynchronous t AOFPD (MIN) DRAM TT,nom asynchronous t AOFPD (MAX) ...
Page 198
... Asynchronous to Synchronous ODT Mode Transition (Power change in the ODT state may be synchronous or asyn- TT 198 to a change in the ODT state can be TT Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Down Exit) ...
Page 199
Figure 116: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command REF NOP NOP NOP CKE t ANPD Short CKE low transition period ( ...
Page 200
... Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef84491df3 1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN Asynchronous to Synchronous ODT Mode Transition (Power- times occur. 200 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2010 Micron Technology, Inc. All rights reserved. Down Exit) ...