MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 119

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Write Leveling Mode Exit Procedure
Figure 44: Write Leveling Exit Procedure
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
R
TT
DQS, R
DQS, DQS#
Command
TT
Address
R
DQS#
TT(DQ)
ODT
CK#
CK
DQ
NOP
T0
Note:
NOP
T1
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 44 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after
ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until
after the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After
mand may be registered by the DRAM. Some MRS commands may be issued after
(at Td1).
t
WLO +
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
R
t
WLOE
TT,nom
NOP
T2
Ta0
NOP
CK = 1
Indicates break
in time scale
NOP
Tb0
ODTLoff
119
t
WLO (MAX) delay plus enough delay to enable the memo-
NOP
Tc0
t
t
AOF (MIN)
AOF (MAX)
1Gb: x8, x16 Automotive DDR3 SDRAM
Undefined Driving Mode
NOP
Tc1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
MRS
MR1
MOD is satisfied (at Te1), any valid com-
Tc2
t
MRD
NOP
Td0
t
IS, ODT must be kept LOW (at
t
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MOD
Valid
Valid
Td1
Transitioning
Write Leveling
NOP
Te0
Don’t Care
Valid
Valid
Te1
t
MOD
t
MRD