MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 143

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

ACTIVATE Operation
Figure 61: Example: Meeting
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command
Address
BA[2:0]
CK#
CK
Bank x
ACT
Row
T0
NOP
T1
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE com-
mand, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the
is programmed correctly, a READ or WRITE command may be issued prior to
(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to
ment that (ACTIVATE-to-READ/WRITE) + AL
Latency).
whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to con-
vert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time in-
terval between successive ACTIVATE commands to the same bank is defined by
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is de-
fined by
t
eter applies, regardless of the number of banks already opened or closed.
FAW (MIN) period, and the
t
RRD
NOP
t
T2
RRD (MIN) and
t
RRD. No more than four bank ACTIVATE commands may be issued in a given
t
RCD (MIN) should be divided by the clock period and rounded up to the next
Bank y
Row
ACT
T3
t
RCD (MIN)
NOP
T4
t
RRD (MIN) restriction still applies. The
143
1Gb: x8, x16 Automotive DDR3 SDRAM
t
RCD specification. However, if the additive latency
NOP
T5
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CCD (MIN).
t
t
RCD (MIN) (see Posted CAS Additive
NOP
RCD
T8
t
RCD (MIN) with the require-
NOP
T9
ACTIVATE Operation
‹ 2010 Micron Technology, Inc. All rights reserved.
Indicates break
in time scale
t
FAW (MIN) param-
NOP
T10
t
RCD
RD/WR
Bank y
Don’t Care
T11
t
Col
RC.