MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 146

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Figure 66 (page 148). DDR3 SDRAM does not allow interrupting or truncating any
READ burst.
Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Fig-
ure 67 (page 148) (BC4 is shown in Figure 68 (page 149)). To ensure the READ data is
completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing
is RL +
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called
cycles later than the READ command. Examples for BL8 are shown in Figure 69
(page 149) and BC4 in Figure 70 (page 150). Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
CHARGE command followed by another PRECHARGE command to the same bank is al-
lowed. However, the precharge period will be determined by the last PRECHARGE com-
mand issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL +
Figure 72 (page 150)). If
auto precharge operation will be delayed until
not satisfied at the edge, the starting point of the auto precharge operation is delayed
until
starts at the point at which the internal precharge happens (not at the next rising clock
edge after this event). The time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (
integer. In any event, internal precharge does not start earlier than four clocks after the
last 8n-bit prefetch.
t
RTP (MIN) is satisfied. In case the internal precharge is pushed out by
t
t
RTP cycles after the READ command. DRAM support a
CCD - WL + 2
t
CK.
t
RAS (MIN) is not satisfied at the edge, the starting point of the
146
1Gb: x8, x16 Automotive DDR3 SDRAM
t
RTP +
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RTP (READ-to-PRECHARGE).
t
RP)*, where * means rounded up to the next
t
RAS (MIN) is satisfied. If
‹ 2010 Micron Technology, Inc. All rights reserved.
t
t
RAS lockout feature (see
RP is met. The PRE-
READ Operation
t
RTP starts AL
t
RTP (MIN) is
t
RTP ,
t
RP