MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 186

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 108: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 109: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
Command
Address
DQS, DQS#
Command
ODT
Address
CK#
R
DQ
CK
TT
ODT
CK#
R
DQ
CK
TT
NOP
T0
NOP
T0
WRS4
Valid
T1
Notes:
Notes:
WRS4
Valid
T1
NOP
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. In this example ODTH4 = 4 is satisfied exactly.
T2
NOP
T2
ODTLcnw
ODTLon
ODTH4
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
ODT can remain HIGH. R
ODTLcnw
ODTLon
ODTH4
NOP
T3
NOP
T3
WL
WL
NOP
T4
NOP
T4
ODTLcwn4
ODTLcwn4
t
AON (MIN)
t
AON (MIN)
t
ADC (MAX)
t
ADC (MAX)
NOP
NOP
T5
TT(WR)
T5
186
is enabled.
1Gb: x8, x16 Automotive DDR3 SDRAM
R
NOP
TT(WR)
NOP
R
T6
T6
DI
DI
n
n
TT(WR)
TT,nom
TT,nom
ODTLoff
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n + 1
n + 1
DI
DI
and R
can be either enabled or disabled. If disabled,
NOP
NOP
n + 2
n + 2
T7
T7
DI
DI
TT(WR)
n + 3
n + 3
DI
DI
NOP
NOP
T8
T8
are enabled.
ODTLoff
t
AOF (MIN)
t
t
AOF (MAX)
ADC (MIN)
t
ADC (MAX)
NOP
T9
NOP
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T9
Transitioning
Transitioning
R
TT,nom
NOP
T10
Dynamic ODT
NOP
T10
Don’t Care
NOP
t
T11
AOF (MIN)
t
AOF (MAX)
NOP
Don’t Care
T11