MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 159

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 81: Consecutive WRITE (BL8) to WRITE (BL8)
Figure 82: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF
Command
DQS, DQS#
Command
DQS, DQS#
Address
Address
DQ
CK#
CK#
DQ
CK
CK
1
2
3
1
2
3
WRITE
WRITE
Valid
Valid
T0
T0
NOP
NOP
T1
T1
Notes:
Notes:
t
t
CCD
CCD
NOP
NOP
T2
T2
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. BC4, WL = 5 (AL = 0, CWL = 5).
3. DI n (or b) = data-in for column n (or column b).
4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
WL = 5
WL = 5
T0 and T4.
NOP
NOP
T3
T3
WRITE
WRITE
Valid
Valid
T4
T4
t
t
WPRE
WPRE
NOP
DI
NOP
T5
n
T5
DI
n
n + 1
n + 1
DI
DI
NOP
n + 2
NOP
n + 2
T6
DI
T6
DI
n + 3
n + 3
WL = 5
WL = 5
DI
DI
t
WPST
n + 4
NOP
NOP
T7
DI
T7
n + 5
DI
NOP
n + 6
NOP
T8
DI
T8
t
WPRE
n + 7
DI
NOP
NOP
DI
DI
T9
T9
b
b
b + 1
b + 1
DI
DI
NOP
T10
NOP
b + 2
T10
b + 2
DI
DI
t
BL = 4 clocks
b + 3
b + 3
DI
DI
t
WPST
t
BL = 4 clocks
NOP
b + 4
T11
T11
NOP
DI
b + 5
DI
NOP
b + 6
T12
NOP
T12
DI
b + 7
Transitioning Data
Transitioning Data
DI
t
WPST
NOP
T13
NOP
T13
t
t
t
t
WR
WTR
WR
WTR
Don’t Care
Don’t Care
NOP
T14
NOP
T14