MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 152

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 73: Data Output Timing –
DQ
3
(first data no longer valid)
DQ
All DQ collectively
3
(last data valid)
Command
DQS, DQS#
Address
CK#
CK
1
2
Notes:
READ
Bank,
Col n
T0
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to V
6.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within
T0.
t
a burst.
NOP
DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.
T1
t
DQSQ and Data Valid Window
NOP
T2
RL = AL + CL
NOP
T3
DDQ
NOP
T4
t
t
DQSQ (MAX)
LZDQ (MIN)
/2 and DLL on and locked.
t
RPRE
NOP
T5
Data valid
DO
t
n
DO
QH
n
DO
n
n + 1
DO
n + 1
DO
n + 1
DO
NOP
T6
n + 2
DO
n + 2
t
DO
DQSQ (MAX)
n + 2
DO
Data valid
n + 3
DO
t
n + 3
QH
DO
n + 3
DO
NOP
T7
n + 4
DO
n + 4
DO
n + 4
DO
n + 5
DO
n + 5
DO
n + 5
DO
NOP
T8
n + 6
DO
n + 6
DO
n + 6
DO
n + 7
t
DO
RPST
n + 7
DO
n + 7
DO
NOP
T9
t
HZDQ (MAX)
NOP
Don’t Care
T10