MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 181

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Dynamic ODT
Dynamic ODT Special Use Case
Table 79: Write Leveling with Dynamic ODT Special Case
Functional Description
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Disable Write Leveling and R
Enable Write Leveling and R
Begin R
MR1 load mode command:
MR1 load mode command:
TT,nom
Uncertainty
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT R
namic ODT R
nominal ODT R
ported by the dynamic ODT feature, as described below.
When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor prefer-
red) by having R
the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur-
ing write accesses.
When enabling this special use case, some standard ODT spec conditions may be viola-
ted: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not
LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this
would appear to be a problem since R
R
locked, then R
when exiting Write Leveling mode. More so, R
Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via
same MR1 load if R
ODT will turn-on within a delay of ODTLon +
or turn-off within a delay of ODTLoff +
between the Load Mode of MR1 and the previously specified delay, the value of ODT is
uncertain. this means the DQ ODT termination could turn-on and then turn-off again
during the period of stated uncertainty.
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so R
namic ODT function is described below:
• Two R
TT(NOM)
– The value for R
– The value for R
TT(NOM)
TT(NOM)
TT
should be used. For Write leveling during this special use case, with the DLL
values are available—R
TT(WR)
TT(NOM)
TT,nom
TT(WR)
TT,nom
TT,nom
TT(WR)
TT(NOM)
) when beginning a WRITE burst and subsequently switches back to
) at the completion of the WRITE burst. This requirement is sup-
ODTLoff +
) enabled, the DRAM switches from nominal ODT R
maybe enabled when entering Write Leveling mode and disabled
ODTLon +
disabled via MR1 and R
End R
is preselected via MR1[9, 6, 2].
is preselected via MR2[10, 9].
is to be used.
181
TT,nom
t
t
AOFF +
AON +
TT,nom
1Gb: x8, x16 Automotive DDR3 SDRAM
Uncertainty
TT(WR)
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
AOF +
t
MOD + 1CK
and R
MOD + 1CK
can not be used (should be disabled) and
TT(NOM)
t
TT(WR)
TT(WR)
AON +
t
MOD + 1CK. As seen in the table below,
.
TT(WR)
enabled via MR2. This will allow
must be enabled when enabling
t
MOD + 1CK (enabling via MR1)
DQS, DQS#
DQS, DQS#
I/Os
DQs
DQs
must be disabled. The dy-
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R
Drive R
TT,nom
Dynamic ODT
No R
No R
No R
TT,nom
TT,nom
Final State
TT,nom
TT,nom
TT,nom
) to dy-
value