MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 124

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 48: Mode Register 0 (MR0) Definitions
Burst Type
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
M15
0
0
1
1
M14
0
1
0
1
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
Mode Register
Note:
ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Accesses within a given burst may be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3] (see Figure 48 (page 124)). The order-
ing of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are re-
stricted to nibble (BC4) or word (BL8) boundaries.
1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to 0.
BA2
0 1
16
M11
M12
15
BA1
0
0
0
0
1
1
1
1
0
0
1
M10
DLL off (slow exit)
0
DLL on (fast exit)
BA0
0
0
1
1
0
0
1
1
14
Precharge PD
M9
0 1
13
0
1
0
1
0
1
0
1
A13
PD
12
Write Recovery
A12 A11
Reserved
Reserved
11
10
12
5
6
7
8
WR
10
A10
M8
0
1
9
A9
DLL Reset
DLL
124
8
A8
Yes
No
M6
0
0
0
0
1
1
1
1
0 1
7
A7 A6 A5 A4 A3
M5
0
0
1
1
0
0
1
1
1Gb: x8, x16 Automotive DDR3 SDRAM
CAS# latency BT
6
M4
0
1
0
1
0
1
0
1
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CAS Latency
4
Reserved
10
11
3
5
6
7
8
9
2
A2 A1 A0
1
0
M3
0
1
M1
0
0
1
1
Address bus
Mode register 0 (MR0)
Mode Register 0 (MR0)
Sequential (nibble)
M0
READ Burst Type
0
1
0
1
Interleaved
4 or 8 (on-the-fly via A12)
‹ 2010 Micron Technology, Inc. All rights reserved.
Fixed BC4 (chop)
Burst Length
Fixed BL8
Reserved