MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 156

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

WRITE Operation
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
WRITE bursts are initiated with a WRITE command. The starting column and bank ad-
dresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is pre-
charged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Fig-
ure 80 (page 158) through Figure 88 (page 163), auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 80 (page 158). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
±
where
(MAX) cases.
Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-
ly. If DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be
following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 81 (page 159) and Figure 82
(page 159) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 83 (page 160).
Data for any WRITE burst may be followed by a subsequent READ command after
has been met (see Figure 84 (page 160), Figure 85 (page 161), and Figure 86
(page 162)).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing
(page 163).
Both
(fixed BC4, BL8 versus OTF).
t
DQSS. Figure 81 (page 159) through Figure 88 (page 163) show the nominal case
t
WTR and
t
DQSS = 0ns; however, Figure 80 (page 158) includes
t
WR has been met, as shown in Figure 87 (page 163) and Figure 88
t
WR starting time may vary, depending on the mode register settings
156
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSS (MIN) and
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WRITE Operation
t
CCD clocks
t
DQSS
t
WTR