MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 114

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MT41J64M16JT-15E AIT:G

Manufacturer Part Number
MT41J64M16JT-15E AIT:G
Description
DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 41: Change Frequency During Precharge Power-Down
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
Command
Address
ODT
CK#
CKE
DM
DQ
CK
NOP
T0
t
AOFPD/
t
t
IH
CH
t
t
CK
AOF
power-down mode
Enter precharge
t
CL
t
IS
Notes:
NOP
Previous clock frequency
T1
t
CPDED
High-Z
High-Z
1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2.
3. If the R
t
CKSRE
NOP
T2
t
tion (ODT) (page 179) for exact requirements).
power-down mode, the ODT signal must be continuously registered LOW, ensuring R
is in an off state. If the R
ing precharge power-down mode, R
be registered LOW or HIGH in this case.
AOFPD and
TT,nom
Ta0
t
CKE
t
Frequency
AOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-
feature was enabled in the mode register prior to entering precharge
change
Tb0
TT,nom
114
t
CKSRX
Tc0
t
IH
t
CH
feature was disabled in the mode register prior to enter-
1Gb: x8, x16 Automotive DDR3 SDRAM
b
t
CK
power-down mode
b
Exit precharge
t
CL
b
t
TT
IS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
Tc1
will remain in the off state. The ODT signal can
Input Clock Frequency Change
New clock frequency
NOP
Td0
t
XP
t
CH
b
t
CK
b
t
CL
DLL RESET
b
MRS
Td1
‹ 2010 Micron Technology, Inc. All rights reserved.
Indicates break
in time scale
t
NOP
DLLK
Te0
t
IH
t
CH
b
t
CK
b
t
CL
b
t
IS
Valid
Valid
Te1
Don’t Care
TT

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