MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 108

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 37: Refresh Mode
SELF REFRESH
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
Command
Address
BA[2:0]
DM
DQ
CK#
CKE
A10
CK
4
4
4
NOP
T0
1
Notes:
One bank
All banks
Bank(s)
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without ex-
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 113)). All power supply inputs
(including V
during self refresh mode operation. All power supply inputs (including V
V
mode operation. V
the following conditions:
• V
• V
• The first WRITE operation may not occur earlier than 512 clocks after V
PRE
T1
REFDQ
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
2. The second REFRESH is not required, but two back-to-back REFRESH commands are
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until
3
SS
REFDQ
ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 169)).
shown.
bank is active (must precharge all active banks).
(MIN) is satisfied.
< V
t
CK
) must be maintained at valid levels upon entry/exit and during self refresh
REFDQ
is valid and stable prior to CKE going back HIGH
NOP
T2
1
REFCA
t
CH
< V
t
RP
t
CL
and V
DD
REFDQ
NOP
T3
is maintained
1
REFDQ
may float or not drive V
108
REF
) must be maintained at valid levels upon entry/exit and
T4
1Gb: x8, x16 Automotive DDR3 SDRAM
t
RFC (MIN)
Valid
NOP
Ta0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
5
5
REF
Ta1
DDQ
2
/2 while in self refresh mode under
Valid
NOP
Tb0
5
5
Indicates break
in time scale
‹ 2010 Micron Technology, Inc. All rights reserved.
t
RFC
2
Valid
NOP
Tb1
5
5
REFCA
Commands
Don’t Care
REFDQ
Tb2
ACT
RA
RA
BA
and
is valid
t
RFC