MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 180

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 77: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
Table 78: ODT Parameters
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Symbol
ODTLoff
ODTLon
t
t
ODTH4
ODTH8
AONPD
AOFPD
t
t
AON
AOF
MR1[9, 6, 2]
110 and 111
000–101
000–101
000
000
ODT minimum HIGH time after ODT
ODT asynchronous turn-off delay
ODT asynchronous turn-on delay
ODT turn-off relative to ODTLoff
ODT turn-on relative to ODTLon
ODT synchronous turn-off delay
ODT synchronous turn-on delay
ODT minimum HIGH time after
assertion or write (BC4)
Notes:
ODT Pin
Description
completion
completion
write (BL8)
0
1
0
1
X
Nominal ODT resistance R
(MR1) Definition. The R
mentioned. DDR3 SDRAM supports multiple R
can be 2, 4, 6, 8, or 12 and RZQ is 240 . R
DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.
Write accesses use R
ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 81 (page 182)). ODT
timings are summarized in Table 78 (page 180), as well as listed in Table 51 (page 68).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 187).
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 181) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
3. ODT must be disabled during reads. The R
for it to be off during writes.
ic ODT is applicable if enabled.
R
TT,nom
DRAM Termination State
R
R
R
R
TT,nom
TT,nom
TT,nom
TT,nom
reserved, ODT on or off
disabled, ODT off
TT,nom
disabled, ODT on
enabled, ODT off
enabled, ODT on
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
or write registration
Write registration
with ODT HIGH
with ODT HIGH
TT,nom
Completion of
Completion of
Begins at
TT,nom
if dynamic ODT (R
ODTLoff
ODTLon
180
termination value applies to the output pins previously
is defined by MR1[9, 6, 2], as shown in Mode Register 1
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT,nom
ODT registered
ODT registered
R
R
Defined to
TT,nom
TT(ON)
TT(OFF)
TT(WR)
Any valid except self refresh, read
Any valid except self refresh, read
R
R
R
R
TT,nom
termination is allowed any time after the
LOW
LOW
TT(OFF)
TT(OFF)
TT(ON)
TT(ON)
value is restricted during writes. Dynam-
±
±
t
) is disabled. If R
t
AON
AOF
On-Die Termination (ODT)
values based on RZQ/n where n
DRAM State
Any valid
Any valid
See Table 51 (page 68)
Illegal
Definition for All
DDR3 Speed Bins
‹ 2010 Micron Technology, Inc. All rights reserved.
0.5
CWL + AL - 2
CWL + AL - 2
t
CK ± 0.2
2–8.5
2–8.5
4
6
TT,nom
t
t
CK
CK
t
CK
is used dur-
Notes
Unit
t
t
t
t
t
CK
CK
ns
ns
CK
CK
ps
CK
2
3
2
3