MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 33

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 15: I
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
I
CKE
External clock
t
t
t
t
t
t
CL
AL
CS#
Command inputs
Row/column addresses
Bank addresses
Data I/O
Output buffer DQ, DQS
ODT
Burst length
Active banks
Idle banks
SRT
ASR
DD
CK
RC
RAS
RCD
RRD
RC
Test
1
DD
Measurement Conditions for I
Notes:
Normal Temperature Range
I
DD6
1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable
Off, CK and CK# = LOW
: Self Refresh Current
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns +
T
Enabled, midlevel
Disabled (normal)
Electrical Specifications – I
C
= 0°C to +85°C
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Disabled
Enabled
LOW
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
DD6
, I
DD6ET
33
Extended Temperature Range
I
DD6ET
, and I
1Gb: x8, x16 Automotive DDR3 SDRAM
Off, CK and CK# = LOW
Enabled (extended)
T
: Self Refresh Current
Enabled, midlevel
Micron Technology, Inc. reserves the right to change products or specifications without notice.
C
DD8
= 0°C to +95°C
DD
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Disabled
Enabled
LOW
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Specifications and Conditions
t
RFC.
‹ 2010 Micron Technology, Inc. All rights reserved.
I
DD8
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
Midlevel
None
: Reset
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
All
2