MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 131

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 52: Mode Register 2 (MR2) Definition
CAS Write Latency (CWL)
Figure 53: CAS Write Latency
AUTO SELF REFRESH (ASR)
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
Note:
WRITE n
T1
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 52 (page 131)). The overall WRITE la-
tency (WL) is equal to CWL + AL (Figure 50 (page 127)).
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
M15
0
0
1
1
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
t
RCD (MIN)
M14
0
1
0
1
M10
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
0
1
1
M9
Mode Register
NOP
0
1
0
1
AL = 5
T2
R
Dynamic ODT
TT(WR)
Reserved
(R
RZQ/4
RZQ/2
TT(WR)
WL = AL + CWL = 11
0 1
BA2
16
disabled
)
15
1
BA1
NOP
14
0
T6
BA0
131
0 1
13
M7
A13
0
1
0 1
12
Self Refresh Temperature
A12 A11
Extended (0°C to 95°C)
M6
Normal (0°C to 85°C)
0
1
1Gb: x8, x16 Automotive DDR3 SDRAM
0 1
11
Enabled: Automatic
Disabled: Manual
Auto Self Refresh
R
CWL = 6
10
TT(WR)
(Optional)
A10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T11
9
A9
0 1
8
A8
SRT
7
A7 A6 A5 A4 A3
ASR
Indicates break
in time scale
6
M5
0
0
0
0
1
1
1
1
5
NOP
CWL
T12
DI
M4
n
0
0
1
1
0
0
1
1
4
M3
Mode Register 2 (MR2)
0
1
0
1
0
1
0
1
3
6 CK (2.5ns t CK • 1.875ns)
7 CK (1.875ns t CK • 1.5ns)
0 1 0 1 0 1
8 CK (1.5ns t CK • 1.25ns)
n + 1
2
CAS Write Latency (CWL)
DI
A2 A1 A0
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5 CK ( t CK • 2.5ns)
Transitioning Data
1
Reserved
Reserved
Reserved
Reserved
0
n + 2
NOP
T13
DI
Address bus
Mode register 2 (MR2)
n + 3
DI
Don’t Care
NOP
T14