MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 85

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
20. The setup and hold times are listed converting the base specification values (to which
21. When the device is operated with input clock jitter, this parameter needs to be derated
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-
24. The maximum preamble is bound by
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-
26. The
27. The maximum postamble is bound by
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-
29.
30. These parameters are measured from a command/address signal transition edge to its
31. For these parameters, the DDR3 SDRAM device supports
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
34. The start of the write recovery time is defined as follows:
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
36. The refresh period is 64ms when T
derating tables apply) to V
of 1 V/ns, are for reference only.
by the actual
deratings are relative to the SDRAM input clock).
rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting
(MIN),
quired to be derated by subtracting
(MAX),
tracting
spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
mands. In addition, after any change of latency
t
slew rate and 2 V/ns CK, CK# differential slew rate.
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
[ns]/
ple, the device will support
cations are met. This means that for DDR3-800 6-6-6, of which
support
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
ternal PRECHARGE command until
• For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When T
though JEDEC specifies
provided that the maximum refresh period is not violated.
IS (base) and
t
t
CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
t
LZDQS (MIN),
t
LZDQ (MAX), and
Electrical Characteristics and AC Operating Conditions
t
t
JITper (MAX), while
nRP = RU(
t
t
JITper (larger of
IH (base) values are for a single-ended 1 V/ns control/command/address
t
RP/
t
LZDQ (MIN), and
t
CK[AVG]) = 6 as long as the input clock jitter specifications are
t
REFI as a MAX, Micron allows REFRESH commands to be burst
85
t
REF
AON (MAX). The parameter
t
nRP (nCK) = RU(
t
when the slew rate is 1 V/ns. These values, with a slew rate
RPRE (MAX) is derated by subtracting
t
1Gb: x8, x16 Automotive DDR3 SDRAM
JITper (MIN) or
C
is greater than 85°C, the refresh period is 32ms. Al-
C
t
RAS (MIN) has been satisfied.
is less than or equal to 85°C. This equates to an aver-
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
ERR10per (MIN):
t
LZDQS (MAX).
t
HZDQS (MAX).
t
AON (MIN). The following parameters are re-
t
RP/
t
JITper (MAX) of the input clock (output
t
t
XPDLL, timing must be met.
CK[AVG]) if all input clock jitter specifi-
t
DQSCK (MAX),
t
RPRE (MIN) is derated by sub-
t
nPARAM (nCK) = RU(
‹ 2010 Micron Technology, Inc. All rights reserved.
t
ERR10per (MAX):
t
RP = 5ns, the device will
t
JITper (MIN).
t
HZ (MAX),
t
PARAM
t
t
WR.
DQSCK
t
LZDQS