MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 117

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Write Leveling Procedure
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, as-
suming the other programable features (MR0, MR1, MR2, and MR3) are first set and the
DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a
High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory con-
troller should attempt to level only one rank at a time; thus, the outputs of other ranks
should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller
may assert ODT after a
sition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon
delay (WL - 2
ment.
The memory controller may drive DQS LOW and DQS# HIGH after
been satisfied. The controller may begin to toggle DQS after
is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a mini-
mum, ODTLon and
After
controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
for a given DQS-to-CK skew. Each DQS toggle must not violate
(MIN) specifications.
during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within
the associated DQS rising edge CK capture within
drive LOW when DQS is toggling must be LOW within
isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an out-
put during this process. Figure 43 (page 118) depicts the basic timing parameters for
the overall write leveling procedure.
The memory controller will most likely sample each applicable prime DQ state and de-
termine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo-
ry controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting is locked, leveling for the rank will have been achieved, and the write leveling
mode for the rank should be disabled or reprogrammed (if write leveling of another
rank follows).
t
WLMRD and a DQS LOW preamble (
t
WLS and
t
CK), provided it does not violate the aforementioned
t
WLH. The prime DQ will output the CK’s status asynchronously from
t
AON must be satisfied at least one clock prior to DQS toggling.
t
DQSL (MAX) and
t
MOD delay, as the DRAM will be ready to process the ODT tran-
117
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSH (MAX) specifications are not applicable
t
WPRE) have been satisfied, the memory
t
WLO. The remaining DQ that always
t
WLOE after the first
t
WLMRD (one DQS toggle
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t
DQSL (MIN) and
t
t
WLDQSEN has
Write Leveling
MOD delay require-
t
WLO is sat-
t
DQSH