MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 184

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 105: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
DQS, DQS#
Figure 106: Dynamic ODT: Without WRITE Command
Command
DQS, DQS#
Command
Address
Address
ODT
CK#
DQ
R
CK
TT
ODT
CK#
DQ
R
CK
TT
NOP
T0
Valid
T0
NOP
T1
Valid
T1
Notes:
Notes:
NOP
T2
ODTLon
ODTH4
NOP
Valid
T3
T2
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
1. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg-
ODTLon
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
istered LOW at T5 is also legal.
t
AON (MIN)
WRS4
Valid
t
T4
AON (MAX)
ODTH4
Valid
T3
t
AON (MIN)
t
AON (MAX)
NOP
T5
ODTLcnw
R
Valid
TT,nom
T4
ODTH4
NOP
T6
TT,nom
WL
Valid
NOP
T7
is enabled and R
T5
ODTLcwn4
t
ADC (MIN)
t
ADC (MAX)
NOP
T8
Valid
T6
TT,nom
NOP
T9
DI
n
R
and R
TT(WR)
TT(WR)
n + 1
DI
Valid
T7
NOP
T10
n + 2
DI
R
TT(WR)
is either enabled or disabled.
TT,nom
n + 3
DI
Valid
NOP
T11
are enabled.
T8
ODTLoff
t
ADC (MIN)
t
ADC (MAX)
T12
NOP
t
AOF (MIN)
Valid
T9
t
AOF (MAX)
Transitioning
NOP
T13
Valid
T10
R
TT,nom
NOP
T14
ODTLoff
Don’t Care
Valid
T11
Transitioning
T15
NOP
NOP
T16
Don’t Care
t
AOF (MIN)
t
AOF (MAX)
NOP
T17