DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet
DSPIC33EP128MC504-I/ML
Specifications of DSPIC33EP128MC504-I/ML
Related parts for DSPIC33EP128MC504-I/ML
DSPIC33EP128MC504-I/ML Summary of contents
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... Contact Lead/Pitch 1.365x.240x.120'' 17.9x7.50x2.05 10.50x7.80x2 Dimensions All dimensions are in millimeters (mm) unless specified. Note: 2011-2012 Microchip Technology Inc. dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/MC20X Timers/Output Compare/Input Capture • 12 general purpose timers: - Five 16-bit and up to two 32-bit timers/counters - Four OC modules configurable as timers/counters ...
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... Yes Yes 35 44 TQFP, QFN TQFP, 16 3/4 Yes Yes 53 64 QFN SPDIP, SOIC, (1) 6 2/3 Yes Yes 21 28 SSOP (4) , QFN-S 8 3/4 Yes Yes 25 36 VTLA VTLA ( 3/4 Yes Yes 35 44 TQFP, QFN TQFP, 16 3/4 Yes Yes 53 64 QFN for details. 2011-2012 Microchip Technology Inc. ...
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... On 28-pin devices, Comparator 4 does not have external connections. Refer to Note 1: Only SPI2 is remappable. 2: INT0 is not remappable. 3: Only the PWM Faults are remappable. 4: The SSOP and VTLA packages are not available for devices with 512 KB of memory. 5: 2011-2012 Microchip Technology Inc. Remappable Peripherals — ...
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... TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL FAMILIES (CONTINUED) Device dsPIC33EP32MC504 512 32 4 dsPIC33EP64MC504 1024 64 8 dsPIC33EP128MC504 1024 128 16 5 dsPIC33EP256MC504 1024 256 32 dsPIC33EP512MC504 1024 512 48 dsPIC33EP64MC506 1024 64 8 dsPIC33EP128MC506 1024 128 16 5 dsPIC33EP256MC506 1024 256 32 dsPIC33EP512MC506 1024 512 48 On 28-pin devices, Comparator 4 does not have external connections. Refer to ...
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... Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See “Peripheral Pin Select” 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 2011-2012 Microchip Technology Inc MCLR AV DD ...
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... PIC24EPXXXGP202 for available peripherals and for information on limitations. = Pins are tolerant RPI45/CTPLS/RB13 21 RPI44/RB12 20 TDI/RP43/RB11 19 18 TDO/RP42/RB10 17 V CAP TMS/ASDA1/SDI1/RP41/RB9 Section 11.4 Section 11.0 2011-2012 Microchip Technology Inc. ...
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... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc dsPIC33EPXXXMC202/502 4 ...
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... PIC24EP32GP203 5 22 PIC24EP64GP203 for available peripherals and for information on limitations. = Pins are tolerant RPI45/CTPLS/RB13 RPI44/RB12 TDI/RP43/RB11 TDO/RP42/RB10 CAP V SS RP56/RC8 TMS/ASDA1/SDI1/RP41/RB9 Section 11.4 Section 11.0 2011-2012 Microchip Technology Inc. ...
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... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc ...
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... PIC24EPXXXGP204 for available peripherals and for information on limitations. = Pins are tolerant SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2 Section 11.4 Section 11.0 2011-2012 Microchip Technology Inc. ...
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... Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See “Peripheral Pin Select” 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 2011-2012 Microchip Technology Inc dsPIC33EPXXXMC204/504 ...
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... dsPIC33EPXXXGP504 PIC24EPXXXGP204 AN8/C3IN1+/U1RTS/BCLK1/RC2 27 26 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 25 PGED1/AN5/C1IN1-/RP35/RB3 24 23 PGEC1/AN4/C1IN1+/RPI34/RB2 for available peripherals and for information on limitations. = Pins are tolerant SS DD Section 11.4 Section 11.0 2011-2012 Microchip Technology Inc. ...
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... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc ...
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... Pins are tolerant SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2 Section 11.4 Section 11.0 2011-2012 Microchip Technology Inc. ...
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... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc ...
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... Pins are tolerant 48 TCK/CV /ASCL1/RP40/T4CK/RB8 REF RC13 46 RP39/INT0/RB7 45 RPI58/RC10 PGEC2/ASCL2/RP38/RB6 44 43 PGED2/ASDA2/RP37/RB5 42 RD8 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CV /SDO1/RP20/T1CK/RA4 REF 2 O Section 11.4 Section 11.0 “I/ 2011-2012 Microchip Technology Inc. ...
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... Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See “Peripheral Pin Select” 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. O Ports” 3: This pin is not available as an input when OPMODE (CMxCON<10> 2011-2012 Microchip Technology Inc ...
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... Pins are tolerant 48 TCK/ CV /ASCL1/RP40/T4CK/RB8 REF RC13 46 RP39/INT0/RB7 45 RPI58/RC10 44 PGEC2/ASCL2/RP38/RB6 43 PGED2/ASDA2/RP37/RB5 42 RD8 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CV /SDO1/RP20/T1CK/RA4 2 REF O Section 11.4 Section 11.0 “I/ 2011-2012 Microchip Technology Inc. ...
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... Ports” 3: This pin is not available as an input when OPMODE (CMxCON<10> The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc dsPIC33EP64MC206/506 5 dsPIC33EP128MC206/506 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70657F-page 20 or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. to receive the most current information on all of our products. 2011-2012 Microchip Technology Inc. ...
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... Section 27. “Programmable Cyclic Redundancy Check (CRC)” (DS70346) • Section 30. “Device Configuration” (DS70618) • Section 32. “Peripheral Trigger Generator (PTG)” (DS70669) • Section 33. “Charge Time Measurement Unit (CTMU)” (DS70661) 2011-2012 Microchip Technology Inc. product page web site 2 C™ ...
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... AND PIC24EPXXXGP/MC20X NOTES: DS70657F-page 22 2011-2012 Microchip Technology Inc. ...
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... QEI1 PWM Peripheral Modules Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices. 2011-2012 Microchip Technology Inc. This document contains device-specific information for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X, and Controller (DSC) and Microcontroller (MCU) devices. ...
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... CTMU external edge input 2. No UART1 clear to send. No UART1 ready to send. Yes UART1 receive. Yes UART1 transmit. No UART1 IrDA baud clock output. Analog = Analog input O = Output TTL = TTL input buffer “Pin Diagrams” Power I = Input section for pin availability. 2011-2012 Microchip Technology Inc. ...
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... This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See 3: Section 16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X for more information. Devices Only)” Not all pins are available in all packages variants. See the 4: 2011-2012 Microchip Technology Inc. PPS Description No UART2 clear to send. No UART2 ready to send. ...
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... CPU logic filter capacitor connection. No Ground reference for logic and I/O pins. No Analog voltage reference (high) input. No Analog voltage reference (low) input. Analog = Analog input O = Output TTL = TTL input buffer “Pin Diagrams” Power I = Input section for pin availability. 2011-2012 Microchip Technology Inc. ...
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... ADC module is implemented The AV and AV Note connected independent of the ADC voltage reference source. 2011-2012 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2011-2012 Microchip Technology Inc. is ...
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... Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749 2011-2012 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. For details, see for details. “ ...
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... Data storage device management • Smart cards and smart card readers Examples of typical application connections are shown SS in Figure 2-4 I PFC V INPUT FET k 2 Driver Op amp/ PWM Comparator Output dsPIC33EP through Figure 2-8. V OUTPUT k 3 ADC Channel 2011-2012 Microchip Technology Inc. ...
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... SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input k 7 ADC Channel FIGURE 2-6: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input FET k 7 Driver ADC Channel dsPIC33EP 2011-2012 Microchip Technology Inc. 5V Output I 5V FET k Driver 1 Op amp/ ADC Comparator Channel dsPIC33EP FET Driver PWM FET ...
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... AN4 AN5 DS70657F-page FET FET Driver Driver Op amp/ Op amp/ PWM PWM Comparator Comparator dsPIC33EP 3-Phase Inverter R49 R41 R34 R36 Fault Demand Phase Terminal Voltage Feedback V + OUT OUT ADC Channel BLDC R44 R52 2011-2012 Microchip Technology Inc. ...
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... These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and was designed for optimum C compiler efficiency. 2011-2012 Microchip Technology Inc. 3.3 Data Space Addressing The base data space can be addressed as 4K words or 8 Kbytes and is split into two blocks, referred and Y data memory ...
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... Logic Logic Y AGU Register Array 16 16 DSP Engine (1) 16 Peripheral Modules X Data Bus Data Latch X Data (1) RAM 24 16 Address Latch RAGU X WAGU (1) EA MUX Divide Support 16-bit ALU 16 Ports 2011-2012 Microchip Technology Inc. ...
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... DOSTARTH , DOSTARTL (1) (1) DOENDH , DOENDL CORCON This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. Note 1: The DOSTARTH and DOSTARTL registers are read-only. 2: 2011-2012 Microchip Technology Inc. for the Figure 3-2. directly by and and 4-1. Description Working register array 40-bit DSP Accumulators ...
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... X Data Space Read Page Address X Data Space Write Page Address Repeat Loop Counter (1) DO Loop Counter and Stack (1) DO Loop Start Address and Stack (1) DO Loop End Address and Stack CPU Core Control Register Status Register 2011-2012 Microchip Technology Inc. ...
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... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 3.6.1 KEY RESOURCES • Section 2. “CPU” (DS70359) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33E/PIC24E Family Reference Manuals Sections • Development Tools 2011-2012 Microchip Technology Inc. DS70657F-page 37 ...
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... SAB bit. To avoid a possible bit write race condition, the SA and SB bits should not be modified using bit operations. DS70657F-page 38 R/W-0 R/C-0 (1,4) (1,4) (1) SB OAB (2,3) R-0 R/W Unimplemented bit, read as ‘0’ Clearable bit ‘0’ = Bit is cleared (1) (1) (1,4) (1,4) (1) (1) R/C R/W-0 (1) (1) SAB DA DC R/W-0 R/W-0 R/W Bit is unknown (1) 2011-2012 Microchip Technology Inc. bit 8 bit 0 ...
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... A data write to the SR register can modify the SA and SB bits by either a data write to SA and clearing the SAB bit. To avoid a possible bit write race condition, the SA and SB bits should not be modified using bit operations. 2011-2012 Microchip Technology Inc. (1,2) DS70657F-page 39 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 3: DS70657F-page 40 R/W-0 R/W-0 (1) (1,2) US<1:0> EDT R/W-0 R/C-0 (1) (1) (3) ACCSAT IPL3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1,2) (1) (1) (1) (1) (3) R-0 R-0 R-0 (1) DL<2:0> bit 8 R-0 R/W-0 R/W-0 (1) (1) SFA RND IF bit Bit is unknown (1) 2011-2012 Microchip Technology Inc. ...
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... Fractional mode enabled for DSP multiply This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 3: 2011-2012 Microchip Technology Inc. (1) (1) DS70657F-page 41 ...
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... DSP INSTRUCTIONS SUMMARY Algebraic ACC Write Operation Back Yes – – y) Yes • change in A Yes • – x • y Yes – x • y 2011-2012 Microchip Technology Inc. ...
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... PROGRAM MEMORY MAP FOR dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X, AND PIC24EP32GP/MC20X DEVICES Memory areas are not shown to scale. Note 1: On reset, these bits are automatically copied into the device Configuration Shadow registers. 2: 2011-2012 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, ...
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... Flash Configuration Bytes 0x00AFFE 0x00B000 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE 2011-2012 Microchip Technology Inc. ...
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... PROGRAM MEMORY MAP FOR dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X, AND PIC24EP128GP/MC20X DEVICES Memory areas are not shown to scale. Note 1: On reset, these bits are automatically copied into the device Configuration Shadow registers. 2: 2011-2012 Microchip Technology Inc. (1) 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 ...
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... Flash Configuration Bytes 0x02AFFE 0x02B000 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE 2011-2012 Microchip Technology Inc. ...
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... PROGRAM MEMORY MAP FOR dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X, AND PIC24EP512GP/MC20X DEVICES Memory areas are not shown to scale. Note 1: On reset, these bits are automatically copied into the device Configuration Shadow registers. 2: 2011-2012 Microchip Technology Inc. (1) 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 ...
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... Flash memory. A more detailed discussion of the interrupt vector tables is provided in Table”. least significant word Instruction Width Section 7.1 “Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 2011-2012 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. 2011-2012 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Memory areas are not shown to scale. Note: DS70657F-page 50 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space Optionally Mapped into Program Memory Space (PSV) ...
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... SFR Space 0x0FFF 0x1001 8 Kbyte 0x1FFF 0x2001 SRAM Space 0x2FFF 0x3001 0x8001 0xFFFF Memory areas are not shown to scale. Note: 2011-2012 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 X Data RAM (X) 0x1FFE 0x2000 Y Data RAM (Y) ...
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... DS70657F-page 52 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE X Data RAM (X) 0x2000 0x2FFE 0x3000 Y Data RAM (Y) 0x4FFE 0x5000 0x8000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space Optionally Mapped into Program Memory Space (PSV) ...
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... Kbyte 0x4FFF 0x5001 SRAM Space 0x7FFF 0x8001 0x8FFF 0x9001 0xFFFF Memory areas are not shown to scale. Note: 2011-2012 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE X Data RAM (X) 0x2000 0x4FFE 0x5000 ...
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... LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE 0x2000 X Data RAM (X) 0x7FFE 0x8000 0x8FFE 0x9000 Y Data RAM (Y) 0xEFFE 0xD000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space Optionally Mapped into Program Memory Space (PSV) ...
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... Address 0x0001 4 Kbyte SFR Space 0x0FFF 0x1001 4 Kbyte SRAM Space 0x1FFF 0x2001 0x8001 0xFFFF Memory areas are not shown to scale. Note: 2011-2012 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 X Data RAM (X) 0x1FFE 0x2000 0x8000 ...
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... Memory areas are not shown to scale. Note: DS70657F-page 56 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 X Data RAM (X) 0x1FFE 0x2000 0x2FFE 0x3000 0x8000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space Optionally Mapped into Program Memory Space (PSV) ...
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... Kbyte SFR Space 0x0FFF 0x1001 0x1FFF 0x2001 16 Kbyte SRAM Space 0x4FFF 0x5001 0x8001 0xFFFF Memory areas are not shown to scale. Note: 2011-2012 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE X Data RAM (X) 0x2000 0x4FFE ...
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... Memory areas are not shown to scale. Note: DS70657F-page 58 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE X Data RAM (X) 0x2000 0x7FFE 0x8000 0x8FFE 0x9000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space Optionally Mapped into Program Memory Space (PSV) ...
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... SFR Space 0x0FFF 0x1001 0x1FFF 0x2001 48 Kbyte SRAM Space 0x7FFF 0x8001 0xEFFF 0xD001 0xFFFF Memory areas are not shown to scale. Note: 2011-2012 Microchip Technology Inc. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE X Data RAM (X) 0x2000 0x7FFE ...
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... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 4.3.1 KEY RESOURCES • Section 4. “Program Memory” (DS70613) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33E/PIC24E Family Reference Manuals Sections • Development Tools Bit-Reversed Bit-Reversed 2011-2012 Microchip Technology Inc. ...
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Special Function Register Maps TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0000 W0 0002 W1 0004 W2 0006 W3 0008 W4 000A W5 ...
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TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0042 0044 CORCON VAR — US<1:0> 0046 XMODEN YMODEN MODCON — ...
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TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name 0000 W0 0002 W1 0004 W2 0006 W3 0008 W4 000A W5 000C W6 000E W7 0010 W8 0012 ...
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TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 — DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 — — — — IFS3 ...
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TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 08C0 NSTDIS OVAERR OVBERR — INTCON2 08C2 GIE DISI SWTRAP — INTCON3 08C4 — — — — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 — DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 — — — — IFS3 ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC36 0888 — PTG0IP<2:0> IPC37 088A — — — — INTCON1 08C0 NSTDIS OVAERR OVBERR — INTCON2 08C2 ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 — DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 — — — — IFS3 ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 08C2 GIE DISI SWTRAP — INTCON3 08C4 — — ...
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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 — DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 — — — — IFS3 ...
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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC36 0888 — PTG0IP<2:0> IPC37 088A — — — — INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE ...
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TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 — DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 — — — — IFS3 ...
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TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC24 0870 — — — — IPC35 0886 — JTAGID<2:0> IPC36 0888 — PTG0IP<2:0> IPC37 088A — — ...
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TABLE 4-8: TIMER1 THROUGH TIMER5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 ...
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TABLE 4-9: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1CON1 0140 — — ICSIDL IC1CON2 0142 — — — — 0144 IC1BUF IC1TMR 0146 IC2CON1 0148 — ...
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TABLE 4-10: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0900 OC1CON1 — — OCSIDL OCTSEL<2:0> OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0904 OC1R 0906 OC1TMR 0908 ...
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TABLE 4-11: PTG REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTGCST 0AC0 PTGEN — PTGSIDL PTGTOGL PTGCON 0AC2 PTGCLK<2:0> PTGBTE 0AC4 PTGHOLD 0AC6 PTGT0LIM 0AC8 PTGT1LIM 0ACA PTGSDLIM 0ACC PTGC0LIM 0ACE PTGC1LIM 0AD0 PTGADJ ...
Page 78
TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 0C00 PTEN — PTSIDL SESTAT PTCON2 0C02 — — — — PTPER 0C04 SEVTCMP 0C06 MDC 0C0A ...
Page 79
TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON2 0C42 PENH PENL POLH POLL FCLCON2 0C44 — CLSRC<4:0> ...
Page 80
TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 QEI1CON 01C0 QEIEN — QEISIDL QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> QEI1STAT 01C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN ...
Page 81
TABLE 4-17: I2C1 and I2C2 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0200 I2C1RCV — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
Page 82
TABLE 4-19: SPI1 and SPI2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0240 — — SPI1STAT SPIEN SPISIDL 0242 — — — SPI1CON1 DISSCK DISSDO MODE16 0244 — SPI1CON2 FRMEN SPIFSD FRMPOL 0248 SPI1BUF ...
Page 83
TABLE 4-20: ADC1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
Page 84
TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — — C1VEC ...
Page 85
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID ...
Page 86
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID 0478 SID<10:3> C1RXF14EID 047A EID<15:8> C1RXF15SID 047C ...
Page 87
TABLE 4-24: CRC REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CRCCON1 0640 CRCEN — CSIDL CRCCON2 0642 — — — CRCXORL 0644 CRCXORH 0646 CRCDATL 0648 CRCDATH 064A CRCWDATL 064C CRCWDATH 064E — = ...
Page 88
TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 0680 — — RPOR1 0682 — — RPOR2 0684 — — RPOR3 0686 — ...
Page 89
TABLE 4-29: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 06A0 — RPINR1 06A2 — — — — RPINR3 06A6 — — — — RPINR7 06AE ...
Page 90
TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 06A0 — RPINR1 06A2 — — — — RPINR3 06A6 — — — — RPINR7 06AE ...
Page 91
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 06A0 — RPINR1 06A2 — — — — RPINR3 06A6 — — — — RPINR7 06AE ...
Page 92
TABLE 4-34: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0728 WR WREN WRERR NVMSIDL NVMADR 072A NVMADRU 072C — — — NVMKEY 072E — — — unknown value on Reset, ...
Page 93
TABLE 4-37: PMD REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name PMD1 0760 T5MD T4MD T3MD T2MD PMD2 0762 — — — — IC4MD PMD3 0764 — — — — PMD4 ...
Page 94
TABLE 4-39: PMD REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name PMD1 0760 T5MD T4MD T3MD T2MD PMD2 0762 — — — — IC4MD PMD3 0764 — — — — PMD4 ...
Page 95
TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0A80 PSIDL — — — CVRCON 0A82 — CVR2OE — — CM1CON 0A84 CON COE CPOL — CM1MSKSRC 0A86 — — — ...
Page 96
TABLE 4-45: DMAC REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0B00 CHEN SIZE DIR HALF DMA0REQ 0B02 FORCE — — — DMA0STAL 0B04 DMA0STAH 0B06 — — — — DMA0STBL 0B08 DMA0STBH 0B0A ...
Page 97
TABLE 4-46: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 0E00 — — — TRISA12 PORTA 0E02 — — — RA12 LATA 0E04 — — — LATA12 ...
Page 98
TABLE 4-49: PORTD REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 0E30 — — — — PORTD 0E32 — — — — LATD 0E34 — — — — ...
Page 99
TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISG 0E60 — — — — PORTG 0E62 — — — — LATG 0E64 — — — — ...
Page 100
TABLE 4-53: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 0E00 — — — — PORTA 0E02 — — — — LATA 0E04 — — — — ...
Page 101
TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 0E00 — — — — PORTA 0E02 — — — — LATA 0E04 — — — — ...
Page 102
TABLE 4-59: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 0E00 — — — — PORTA 0E02 — — — — LATA 0E04 — — — — ...
Page 103
... EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION EA<15> (DSRPAG = don't care) Generate PSV address Note: DS read access when DSRPAG = 0x000 will force an Address Error trap. 2011-2012 Microchip Technology Inc. Construction of the EDS address is shown in Figure 4-1. When DSRPAG<9> and base address bit EA<15> DSRPAG<8:0> is concatenated onto architecture EA< ...
Page 104
... DSWPAG is dedicated to DS, including EDS, only. The data space and EDS can be read from and written to using DSRPAG and DSWPAG, respectively. DS70657F-page 104 16-bit EDS access EA 0 EA<15> DSWPAG<8:0> 9 bits 15 bits 24-bit EDS EA 2011-2012 Microchip Technology Inc. Byte Select Byte Select ...
Page 105
EXAMPLE 4-3: PAGED DATA MEMORY SPACE Local Data Space DS_Addr<14:0> 0x0000 0x7FFF 0x0000 0x7FFF DS_Addr<15:0> 0x0000 0x0000 SFR Registers 0x0FFF 0x7FFF 0x1000 0x0000 Kbyte RAM 0x7FFF 0x2FFF 0x3000 0x7FFF 0x8000 32 Kbyte 0x0000 EDS Window 0xFFFF 0x7FFF ...
Page 106
... DSRPAG = 0x2FF 1 page Table 4-61 lists the effects of underflow scenarios at different After DS Page EA<15> Description See Note 1 0 PSV: First MSB 1 page See Note 1 0 See Note 1 0 See Note 1 0 See Note 1 0 PSV: Last lsw 1 page 2011-2012 Microchip Technology Inc. ...
Page 107
... SFR/DS Conventional DS Address 0x8000 DS 0xFFFF 2011-2012 Microchip Technology Inc. The remaining pages including both EDS and PSV pages are only accessible using the DSRPAG or DSWPAG registers in combination with the upper 32 Kbytes, 0x8000 to 0xFFFF, of the base address, where base address bit EA<15> ...
Page 108
... All other values of MSTRPR<15:0> are Note 1: Reserved. ICD Reserved DMA Data Memory Arbiter SRAM DATA MEMORY BUS ARBITER PRIORITY (1) MSTRPR<15:0> Bit Setting 0x0000 0x0020 CPU DMA Reserved CPU Reserved Reserved DMA Reserved ICD ICD CPU M4 2011-2012 Microchip Technology Inc. ...
Page 109
... Stack Frame Pointer (SFA = 1 the stack can be placed in, and can access, X and Y spaces, care must be taken regarding its use, particularly with regard to local automatic variables development environment 2011-2012 Microchip Technology Inc. FIGURE 4-19: 0x0000 15 b‘000000000’ 4.5 Instruction Addressing Modes ...
Page 110
... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ULNK, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. 2011-2012 Microchip Technology Inc. ...
Page 111
... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2011-2012 Microchip Technology Inc. 4.6.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: ...
Page 112
... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. 2011-2012 Microchip Technology Inc. N bytes, bit-reversed ...
Page 113
... Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address ...
Page 114
... Program Space Address <23> <22:16> 0 0xx xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx Program Counter 0 23 bits TBLPAG 1/0 8 bits 24 bits <15> <14:1> <0> PC<22:1> 0 xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx 0 EA 1/0 16 bits Byte Select 2011-2012 Microchip Technology Inc. ...
Page 115
... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2011-2012 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
Page 116
... AND PIC24EPXXXGP/MC20X NOTES: DS70657F-page 116 2011-2012 Microchip Technology Inc. ...
Page 117
... Program Counter Using 1/0 Table Instruction User/Configuration Space Select 2011-2012 Microchip Technology Inc. programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V Master Clear (MCLR). This allows customers to and manufacture boards with unprogrammed devices and ...
Page 118
... The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA. (Register 5-1) controls which 5- write-only register that is the user application must 2011-2012 Microchip Technology Inc. ...
Page 119
... Flash memory becomes operational. All other combinations of NVMOP<3:0> are unimplemented. 3: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. 4: Two adjacent words on a 4-word boundary are programmed during execution of this operation. 5: 2011-2012 Microchip Technology Inc. (1) R/W-0 U-0 (2) NVMSIDL — ...
Page 120
... NVMADR<15:8> R/W-x R/W-x R/W-x NVMADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-x R/W-x bit Bit is unknown R/W-x R/W-x bit 8 R/W-x R/W-x bit Bit is unknown U-0 U-0 — ...
Page 121
... V DD Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch 2011-2012 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of Reset will make the SYSRST sig- nal active. On system Reset, some of the registers and ...
Page 122
... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 6.1.1 KEY RESOURCES • Section 8. “Reset” (DS70602) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33E/PIC24E Family Reference Manuals Sections • Development Tools DS70657F-page 122 2011-2012 Microchip Technology Inc. ...
Page 123
... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not Note 1: cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the 2: SWDTEN bit setting. 2011-2012 Microchip Technology Inc. (1) U-0 R/W-0 — VREGSF ...
Page 124
... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not Note 1: cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the 2: SWDTEN bit setting. DS70657F-page 124 (1) (CONTINUED) 2011-2012 Microchip Technology Inc. ...
Page 125
... Interrupt Vector Table (IVT) with a unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Fixed interrupt entry and return latencies 2011-2012 Microchip Technology Inc. 7.1 Interrupt Vector Table The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X, and PIC24EPXXXGP/MC20X Interrupt Vector ...
Page 126
... Interrupt Vector 245 START OF CODE DS70657F-page 126 0x000000 0x000002 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 Reserved 0x000012 0x000014 0x000016 : : : : : : 0x00007C 0x00007E 0x000080 : : : : : : 0x0000FC 0x0000FE 0x000100 0x000102 0x000104 : : : : : : 0x0001FC 0x0001FE 0x000200 See Table 7-1 for Interrupt Vector details 2011-2012 Microchip Technology Inc. ...
Page 127
... PSEM – PWM Special Event Match QEI1 – QEI1 Position Counter Compare This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. Note 1: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: 2011-2012 Microchip Technology Inc. Vector IRQ IVT Address # # Highest Natural Order Priority ...
Page 128
... IFS6<0> IEC6<0> IPC24<2:0> — — — IFS8<14> IEC8<14> IPC35<10:8> IFS8<15> IEC8<15> IPC35<14:12> — — — IFS9<1> IEC9<1> IPC36<6:4> IFS9<2> IEC9<2> IPC36<10:8> IFS9<3> IEC9<3> IPC36<14:12> IFS9<4> IEC9<4> IPC37<2:0> IFS9<5> IEC9<5> IPC37<6:4> IFS9<6> IEC9<6> IPC37<10:8> — — — 2011-2012 Microchip Technology Inc. ...
Page 129
... DO stack overflow status trap sources. The INTCON4 register contains generated hard trap status bit (SGHT). 2011-2012 Microchip Technology Inc. 7.4.2 IFSx The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software ...
Page 130
... The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15> DS70657F-page 130 (1) R/W-0 R/C-0 SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Clearable bit ‘0’ = Bit is cleared (2,3) Register 3-1. R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 131
... IPL3: CPU Interrupt Priority Level Status bit CPU interrupt priority level is greater than CPU interrupt priority level less For complete register details, see Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. 2: 2011-2012 Microchip Technology Inc. (1) R/W-0 R/W-0 US<1:0> EDT R/W-0 ...
Page 132
... This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. Note 1: DS70657F-page 132 R/W-0 R/W-0 (1) (1) (1) COVAERR COVBERR OVATE R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) (1) R/W-0 R/W-0 R/W-0 (1) (1) (1) OVBTE COVTE bit 8 R/W-0 R/W-0 U-0 OSCFAIL — bit Bit is unknown (1) (1) 2011-2012 Microchip Technology Inc. ...
Page 133
... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. Note 1: 2011-2012 Microchip Technology Inc. DS70657F-page 133 ...
Page 134
... INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70657F-page 134 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
Page 135
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-1 Unimplemented: Read as ‘0’ bit 0 SGHT: Software Generated Hard Trap Status bit 1 = Software generated hard trap has occurred 0 = Software generated hard trap has not occurred 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...
Page 136
... Math Error Trap 00000011 = 3, Stack Error Trap 00000010 = 2, Generic Hard Trap 00000001 = 1, Address Error Trap 00000000 = 0, Oscillator Fail Trap DS70657F-page 136 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 137
... FIGURE 8-1: DMA CONTROLLER PERIPHERAL 2011-2012 Microchip Technology Inc. The DMA controller transfers data between peripheral data registers and data space SRAM In addition, DMA can access the entire data memory space. The Data Memory Bus Arbiter is utilized when ...
Page 138
... Microchip Technology Inc. ...
Page 139
... Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33E/PIC24E Family Reference Manuals Sections • Development Tools 2011-2012 Microchip Technology Inc. Peripheral Indirect Address DMA Controller DMA Channels DMA X-Bus CPU Peripheral X-Bus ...
Page 140
... One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled DS70657F-page 140 CONTROL REGISTER X R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ‘ ’ 0 ‘ ’ 0 U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 141
... INT0 – External Interrupt 0 The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the Note 1: forced DMA transfer is complete or the channel is disabled (CHEN = 0). This selection is available in dsPIC33EPXXXGP/MC50X devices only. 2: 2011-2012 Microchip Technology Inc. IRQ SELECT REGISTER X U-0 U-0 U-0 — ...
Page 142
... R/W-0 STA<23:16> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared START ADDRESS REGISTER A (LOW) X R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 143
... R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary Start Address bits (source or destination) 2011-2012 Microchip Technology Inc. START ADDRESS REGISTER B (HIGH) X U-0 R/W-0 U-0 — — — R/W-0 R/W-0 R/W-0 STB<23:16> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 144
... PAD<15:8> R/W-0 R/W-0 R/W-0 PAD<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared TRANSFER COUNT REGISTER X R/W-0 R/W-0 R/W-0 (2) CNT<13:8> R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) 2011-2012 Microchip Technology Inc. (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 145
... DSADRL: MOST RECENT RAM LOW ADDRESS REGISTER R-0 R-0 R-0 bit 15 R-0 R-0 R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits 2011-2012 Microchip Technology Inc. U-0 R/W-0 U-0 — — — R-0 R-0 R-0 DSADR<23:16> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 R-0 DSADR< ...
Page 146
... PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected write collision detected DS70657F-page 146 U-0 U-0 U-0 — — — U-0 R-0 R-0 — PWCOL3 PWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 PWCOL1 PWCOL0 bit Bit is unknown ...
Page 147
... RQCOL1: Channel 1 Transfer Request Collision Flag bit 1 = User FORCE and Interrupt-based request collision detected request collision detected bit 0 RQCOL0: Channel 0 Transfer Request Collision Flag bit 1 = User FORCE and Interrupt-based request collision detected request collision detected 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 148
... Last data transfer was handled by Channel 1 0000 = Last data transfer was handled by Channel 0 DS70657F-page 148 U-0 U-0 U-0 — — — U-0 R-1 R-1 — LSTCH<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R-1 R-1 bit Bit is unknown ...
Page 149
... DMASTB2 register selected 0 = DMASTA2 register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMASTB1 register selected 0 = DMASTA1 register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMASTB0 register selected 0 = DMASTA0 register selected 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 R-0 R-0 — ...
Page 150
... AND PIC24EPXXXGP/MC20X NOTES: DS70657F-page 150 2011-2012 Microchip Technology Inc. ...
Page 151
... F and F are used interchangeably, except in the case of DOZE mode used with a doze ratio of 1:2 or lower. 2011-2012 Microchip Technology Inc. The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X, and PIC24EPXXXGP/MC20X oscillator system provides: • On-chip Phase-Locked Loop (PLL) to boost inter- and nal operating frequency on select internal and ...
Page 152
... IN OSC provides the relation between input ) and VCO frequency ( SYS 120 MHz @ +125ºC F OSC 140 MHz @ +85º OSC F OSC ÷ N2 2 PLLPOST + 1 2011-2012 Microchip Technology Inc. ...
Page 153
... KEY RESOURCES • Section 7. “Oscillator” (DS70580) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33E/PIC24E Family Reference Manuals Sections • Development Tools 2011-2012 Microchip Technology Inc. Oscillator Source POSCMD<1:0> FNOSC<2:0> Internal xx Internal xx Primary 10 ...
Page 154
... PLL modes. Reset values for these bits are determined by the FNOSC Configuration bits. 3: DS70657F-page 154 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/W-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) 2011-2012 Microchip Technology Inc. R/W-y R/W-y (2,3) bit 8 U-0 R/W-0 — OSWEN bit Bit is unknown ...
Page 155
... This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. Reset values for these bits are determined by the FNOSC Configuration bits. 3: 2011-2012 Microchip Technology Inc. (1) (CONTINUED) DS70657F-page 155 ...
Page 156
... The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to 3: set the DOZEN bit is ignored. DS70657F-page 156 R/W-1 R/W-0 R/W-0 (2) (1,3) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1,3) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 157
... DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to 2: DOZE<2:0> are ignored. The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to 3: set the DOZEN bit is ignored. 2011-2012 Microchip Technology Inc. DS70657F-page 157 ...
Page 158
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 DS70657F-page 158 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 159
... Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) • • • 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> ...
Page 160
... This pin is remappable. See 2: DS70657F-page 160 R/W-0 R/W-0 ROSEL U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) pin (1) Section 11.4 “Peripheral Pin Select” R/W-0 R/W-0 R/W-0 (1) RODIV<3:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown for more information. 2011-2012 Microchip Technology Inc. ...
Page 161
... EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into Sleep mode PWRSAV #IDLE_MODE ; Put the device into Idle mode 2011-2012 Microchip Technology Inc. 10.1 Clock Frequency and Clock Switching The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ and 50X, and PIC24EPXXXGP/MC20X devices allow a ...
Page 162
... TSIDL bit in the Timer1 Control register (T1CON<13>). 10.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 2011-2012 Microchip Technology Inc. ...
Page 163
... Doze mode with a clock frequency ratio of 1:4, the ECAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS. 2011-2012 Microchip Technology Inc. 10.4 Peripheral Module Disable power The Peripheral Module Disable (PMD) registers ...
Page 164
... This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: DS70657F-page 164 R/W-0 R/W-0 R/W-0 (1) T2MD T1MD QEI1MD R/W-0 R/W-0 U-0 SPI2MD SPI1MD — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) 2011-2012 Microchip Technology Inc. R/W-0 U-0 (1) PWMMD — bit 8 R/W-0 R/W-0 (2) C1MD AD1MD bit Bit is unknown ...
Page 165
... ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Note 1: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: 2011-2012 Microchip Technology Inc. (2) DS70657F-page 165 ...
Page 166
... OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70657F-page 166 U-0 R/W-0 R/W-0 — IC4MD IC3MD U-0 R/W-0 R/W-0 — OC4MD OC3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 167
... REFOMD: Reference Clock Module Disable bit 1 = Reference Clock module is disabled 0 = Reference Clock module is enabled bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 1-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...
Page 168
... This bit is available in dsPIC33EPXXXMC50X/20X and PIC24EPXXXMC20X devices only. Note 1: DS70657F-page 168 U-0 U-0 R/W-0 (1) — — PWM3MD U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) (1) PWM2MD PWM1MD bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 169
... DMA3 module is disabled 0 = DMA3 module is enabled bit 3 PTGMD: PTG Module Disable bit 1 = PTG module is disabled 0 = PTG module is enabled bit 2-0 Unimplemented: Read as ‘0’ This single bit enables and disables all four DMA channels. Note 1: 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 ...
Page 170
... AND PIC24EPXXXGP/MC20X NOTES: DS70657F-page 170 2011-2012 Microchip Technology Inc. ...
Page 171
... WR Port Data Latch Read LAT Read Port 2011-2012 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...
Page 172
... EXAMPLE 11-1: MOV 0xFF00 converted OL MOV W0, TRISB NOP BTSS PORTB, #13 11-1. PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> outputs ; Delay 1 cycle ; Next Instruction 2011-2012 Microchip Technology Inc. ...
Page 173
... Microchip Technology Inc. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. ...
Page 174
... DTCMP3 RPINR39 to the QEI module allows illustrates how the input Configuration Bits INT1R<6:0> INT2R<6:0> T2CKR<6:0> IC1R<6:0> IC2R<6:0> IC3R<6:0> IC4R<6:0> OCFAR<6:0> FLT1R<6:0> FLT2R<6:0> QEA1R<6:0> QEB1R<6:0> INDX1R<6:0> HOM1R<6:0> U1RXR<6:0> U2RXR<6:0> SDI2R<6:0> SCK2R<6:0> SS2R<6:0> C1RXR<6:0> SYNCI1R<6:0> DTCMP1R<6:0> DTCMP2R<6:0> DTCMP3R<6:0> 2011-2012 Microchip Technology Inc. ...
Page 175
... Legend: Shaded rows indicate PPS input register values that are unimplemented. See Note 1: Section 11.4.4.1 “Virtual Connections” These inputs are available on dsPIC33EPXXXGP/MC50X devices only. 2: 2011-2012 Microchip Technology Inc. Peripheral Pin Select Input Register Value Vss 010 1101 (1) C1OUT ...
Page 176
... I/O RP118 I RPI119 I/O RP120 I RPI121 — — — — — — — — — — — — 2011-2012 Microchip Technology Inc. ...
Page 177
... QEI1CCMP 101111 REFCLKO 110001 C4OUT 110010 This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Note 1: This function is available in dsPIC33EPXXXGP/MC50X devices only. 2: 2011-2012 Microchip Technology Inc. FIGURE 11-3: Default U1TX Output SDO2 Output 11-27). The QEI1CCMP Output REFCLKO Output 11.4.4.3 Mapping Limitations The control schema of the peripheral select pins is not limited to a small range of fixed peripheral configura- tions ...
Page 178
... characteristic specifica and I current rating only OH OL and at or below the V levels levels. An I/O pin out and graphs for 2011-2012 Microchip Technology Inc. ...
Page 179
... Microchip Technology Inc. 11.6 I/O Ports Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet ...
Page 180
... Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’ DS70657F-page 180 R/W-0 R/W-0 R/W-0 INT1R<6:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS R/W-0 R/W-0 bit 8 U-0 U-0 — — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 181
... INT2R<6:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT2R<6:0> Unimplemented bit, read as ‘0’ ...
Page 182
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 182 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 T2CKR<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 183
... IC1R<6:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC2R<6:0> R/W-0 R/W-0 R/W-0 IC1R<6:0> Unimplemented bit, read as ‘0’ ...
Page 184
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 184 R/W-0 R/W-0 R/W-0 IC4R<6:0> R/W-0 R/W-0 R/W-0 IC3R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 185
... OCFAR<6:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 OCFAR<6:0> Unimplemented bit, read as ‘0’ ...
Page 186
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 186 R/W-0 R/W-0 R/W-0 FLT2R<6:0> R/W-0 R/W-0 R/W-0 FLT1R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 187
... QEA1R<6:0>: Assign A (QEA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 QEB1R<6:0> R/W-0 R/W-0 R/W-0 QEA1R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 188
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 188 R/W-0 R/W-0 R/W-0 HOME1R<6:0> R/W-0 R/W-0 R/W-0 INDX1R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 189
... U1RXR<6:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 U1RXR<6:0> Unimplemented bit, read as ‘0’ ...
Page 190
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 190 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 U2RXR<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 191
... SDI2<6:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SCK2<6:0> R/W-0 R/W-0 R/W-0 SDI2<6:0> Unimplemented bit, read as ‘0’ ...
Page 192
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 192 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 SS2<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 193
... C1RXR<6:0>: Assign CAN1 RX Input (CRX1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 C1RXR<6:0> Unimplemented bit, read as ‘0’ ...
Page 194
... Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’ DS70657F-page 194 R/W-0 R/W-0 R/W-0 SYNCI1R<6:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS R/W-0 R/W-0 bit 8 U-0 U-0 — — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 195
... DTCMP1R<6:0>: Assign PWM Dead Time Compensation Input 1 to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DTCMP1R<6:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
Page 196
... Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V DS70657F-page 196 R/W-0 R/W-0 R/W-0 DTCMP3R<6:0> R/W-0 R/W-0 R/W-0 DTCMP2R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 197
... Unimplemented: Read as ‘0’ bit 13-8 RP37R<5:0>: Peripheral Output Function is Assigned to RP37 Output Pin bits (see peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP36R<5:0>: Peripheral Output Function is Assigned to RP36 Output Pin bits (see peripheral function numbers) 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP35R<5:0> R/W-0 R/W-0 R/W-0 RP20R<5:0> ...
Page 198
... R/W-0 RP39R<5:0> R/W-0 R/W-0 R/W-0 RP38R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP41R<5:0> R/W-0 R/W-0 R/W-0 RP40R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-3 for Table 11-3 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 199
... Unimplemented: Read as ‘0’ bit 13-8 RP55R<5:0>: Peripheral Output Function is Assigned to RP55 Output Pin bits (see peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP54R<5:0>: Peripheral Output Function is Assigned to RP54 Output Pin bits (see peripheral function numbers) 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP43R<5:0> R/W-0 R/W-0 R/W-0 RP42R<5:0> ...
Page 200
... RP57R<5:0> R/W-0 R/W-0 R/W-0 RP56R<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP97R<5:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-3 for Table 11-3 for R/W-0 R/W-0 bit 8 U-0 U-0 — — ...