DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 252

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
17.2
REGISTER 17-1:
DS70657F-page 252
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-4
Note 1:
QEIEN
R/W-0
U-0
—
2:
3:
QEI Control Registers
When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
When CCM = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
PIMOD<2:0>: Position Counter Initialization Mode Select bits
111 = Reserved
110 = Modulo count mode for position counter
101 = Resets the position counter when the position counter equals QEI1GEC register
100 = Second index event after home event initializes position counter with contents of QEI1IC
011 = First index event after home event initializes position counter with contents of QEI1IC register
010 = Next index input event initializes the position counter with contents of QEI1IC register
001 = Every Index input event resets the position counter
000 = Index input event does not affect position counter
IMV<1:0>: Index Match Value bits
11 = Index match occurs when QEB = 1 and QEA = 1
10 = Index match occurs when QEB = 1 and QEA = 0
01 = Index match occurs when QEB = 0 and QEA = 1
00 = Index input event does not affect position counter
Unimplemented: Read as ‘0’
INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter),
velocity counter and index counter internal clock divider select)
111 = 1:128 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
R/W-0
U-0
—
QEI1CON: QEI CONTROL REGISTER
register
INTDIV<2:0>
W = Writable bit
‘1’ = Bit is set
QEISIDL
R/W-0
R/W-0
(3)
R/W-0
R/W-0
(2)
PIMOD<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CNTPOL
R/W-0
R/W-0
(1)
GATEN
R/W-0
R/W-0
(1)
(3)
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
IMV<1:0>
CCM<1:0>
(2)
R/W-0
R/W-0
bit 8
bit 0