DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 273

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

19.0
 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 19. “Inter-Inte-
grated Circuit™ (I
the “dsPIC33E/PIC24E Family Refer-
ence Manual”, which is available from the
Microchip
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
2
C™)
dsPIC33EPXXXGP50X,
2
C™)” (DS70330) of
web
families
and
site
of
in
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X family of devices
contain two Inter-Integrated Circuit (I
and I2C2.
The I
for both Slave and Multi-Master modes of the I
communication standard, with a 16-bit interface.
The I
• The SCLx pin is clock.
• The SDAx pin is data.
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
• Intelligent Platform Management Interface (IPMI)
• System Management Bus (SMBus) support
modes of operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and arbitrates accordingly.
support
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
2
C module has a 2-pin interface:
C module offers the following key features:
C module provides complete hardware support
2
DS70657F-page 273
C port can be
2
C) modules: I2C1
2
C serial