DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 354

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
25.1
There are two configurations to take into consideration
when designing with the Op amp modules that are
available
dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/
MC20X devices. Configuration A (see
takes advantage of the internal connection to the ADC
module to route the output of the Op amp directly to the
ADC
Figure
the output of the Op amp (OAxOUT) to a separate ana-
log input pin (ANx) on the device.
Section 30.0 “Electrical Characteristics”
the performance characteristics for the Op amps, dis-
tinguishing between the two configuration types where
applicable.
FIGURE 25-5:
DS70657F-page 354
Note 1: See
Voltage
25-6) requires that the designer externally route
for
Bias
2: See
3: See
4: CV
Op amp Application
Considerations
V
IN
measurement.
(4)
in
REF
Table 30-52
Table 30-52
Table 30-59
1
O
R
the
or CV
OP AMP CONFIGURATION A
1
REF
for the Typical value.
for the Minimum value for the feedback resistor.
and
Configuration
dsPIC33EPXXXGP50X,
2
V
CxIN1-
CxIN1+
O
ADC
V
Table 30-60
OAxOUT
are two options that are available for supplying bias voltage to the op amps.
=
Table 30-54


R
-------------------------------------------------- -
Figure
FEEDBACK
=
describes


B
for the minimum sample time (T
R
----------------------------- -
FEEDBACK
25-5)
(see
R
R
1
in
Op ampx
1
–
+
+
R
INT1
 Bias Voltage V


 Bias Voltage V


25.1.1
Figure 25-5
taking advantage of the internal connections from the
Op amp output to the input of the ADC. The advantage
of this configuration is that the user does not need to
consume another analog input (ANx) on the device,
and allows the user to simultaneous sample all three
Op amps with the ADC module, if needed. However,
the presence of the internal resistance, R
error in the feedback path. Since R
resistance, in relation to the Op amp output (V
and ADC internal connection (V
included in the numerator term of the transfer function.
See
teristics”
and
teristics”
requirements for the ADC module in this configuration.
Figure 25-5
used when calculating the expected voltages at points
V
ADC
ADC
V
ADC
R
Table 30-60
Table 30-52
(3)
and V
FEEDBACK (2)
–
describe the minimum sample time (T
for the typical value of R
OA
OP AMP CONFIGURATION A
also defines the equations that should be
shows a typical inverting amplifier circuit
–
IN
X
SAMP
(to ADC)
OUT
OAx
IN

in
in
R
 2011-2012 Microchip Technology Inc.
.

INT
).
Section 30.0 “Electrical Charac-
Section 30.0 “Electrical Charac-
1
(1)
ADC
(V
OAxOUT
OA
INT
INT
), R
X
1 is an internal
OUT
1.
INT
INT
Table 30-59
)
1 must be
1, adds an
OA x OUT
SAMP
)
)