DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 491

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

APPENDIX A:
Revision A (April 2011)
This is the initial released version of the document.
Revision B (July 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in
TABLE A-1:
 2011-2012 Microchip Technology Inc.
“High-Performance, 16-bit
Digital Signal Controllers
and Microcontrollers”
Section 4.0 “Memory
Organization”
Section 5.0 “Flash Program
Memory”
Section 9.0 “Oscillator
Configuration”
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Section 25.0 “Op amp/
Comparator Module”
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
Section Name
MAJOR SECTION UPDATES
Table
REVISION HISTORY
A-1.
Changed all pin diagrams references of VLAP to TLA.
Updated the All Resets values for CLKDIV and PLLFBD in the System Control
Register Map (see Table 4-35).
Updated “one word” to “two words” in the first paragraph of Section 5.2 “RTSP
Operation”.
Updated the PLL Block Diagram (see Figure 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL
(FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and
NOSC<2:0> = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the
FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default
definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions
for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default
definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see
Register 9-2).
Updated the bit definitions for the IRNG<1:0> bits in the CTMU Current Control
Register (see Register 22-3).
Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2).
Update Description
DS70657F-page 491