DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 95

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

TABLE 4-42:
TABLE 4-43:
TABLE 4-44:
CMSTAT
CVRCON
CM1CON
CM1MSKSRC 0A86
CM1MSKCON 0A88
CM1FLTR
CM2CON
CM2MSKSRC 0A8E
CM2MSKCON 0A90
CM2FLTR
CM3CON
CM3MSKSRC 0A96
CM3MSKCON 0A98
CM3FLTR
CM4CON
CM4MSKSRC 0A9E
CM4MSKCON 0AA0
CM4FLTR
Legend:
CTMUCON1 033A
CTMUCON2 033C
CTMUICON
Legend:
JDATAH
JDATAL
File Name
File Name
File Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
033E
Addr
0FF0
0FF2
Addr.
0A8A
0A8C
0A9A
0A9C
0AA2
0A80
0A82
0A84
0A92
0A94
EDG1MOD EDG1POL
OP AMP/COMPARATOR REGISTER MAP
CTMU REGISTER MAP
JTAG INTERFACE REGISTER MAP
CTMUEN
PSIDL
Bit 15
Bit 15
HLMS
HLMS
HLMS
HLMS
CON
CON
CON
CON
Bit 15
—
—
—
—
—
—
—
—
—
—
CVR2OE
Bit 14
Bit 14
COE
COE
COE
COE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 14
—
OCEN
OCEN
OCEN
OCEN
Bit 13
CPOL
CPOL
CPOL
CPOL
Bit 13
CTMUSIDL TGEN
—
—
—
—
—
—
—
—
—
—
—
Bit 13
ITRIM<5:0>
—
OCNEN
OCNEN
OCNEN
OCNEN
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 12
—
C4EVT
OBEN
OBEN
OBEN
OBEN
Bit 11
Bit 11
EDGEN EDGSEQEN
—
—
—
—
—
—
—
—
—
Bit 11
EDG1SEL<1:0>
VREFSEL
OPMODE
OPMODE
OPMODE
OBNEN
OBNEN
OBNEN
OBNEN
C3EVT
Bit 10
Bit 10
SELSRCC<3:0>
SELSRCC<3:0>
SELSRCC<3:0>
SELSRCC<3:0>
—
—
—
—
—
Bit 10
C2EVT
Bit 9
CEVT
OAEN
CEVT
OAEN
CEVT
OAEN
CEVT
OAEN
Bit 9
EDG2STAT EDG1STAT EDG2MOD EDG2POL
—
—
—
—
—
IDISSEN
Bit 9
IRNG<1:0>
Bit 8
OANEN
OANEN
OANEN
OANEN
C1EVT
JDATAL<15:0>
COUT
COUT
COUT
COUT
Bit 8
—
—
—
—
—
CTTRIG
Bit 8
Bit 7
CVREN CVR1OE
NAGS
NAGS
NAGS
NAGS
Bit 7
EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
—
—
—
—
—
Bit 7
—
—
JDATAH<27:16>
Bit 6
SELSRCB<3:0>
SELSRCB<3:0>
SELSRCB<3:0>
SELSRCB<3:0>
PAGS
PAGS
PAGS
PAGS
Bit 6
—
CFSEL<2:0>
CFSEL<2:0>
CFSEL<2:0>
CFSEL<2:0>
Bit 6
—
—
Bit 5
CVRR
ACEN
ACEN
ACEN
ACEN
Bit 5
—
—
—
—
—
Bit 5
CVRSS
ACNEN
ACNEN
ACNEN
ACNEN
—
—
—
CREF
CREF
CREF
CREF
Bit 4
Bit 4
—
Bit 4
CFLTREN
CFLTREN
CFLTREN
CFLTREN
—
—
—
C4OUT
Bit 3
ABEN
ABEN
ABEN
ABEN
Bit 3
—
—
—
—
EDG2SEL<1:0>
Bit 3
—
—
C3OUT
ABNEN
ABNEN
ABNEN
ABNEN
Bit 2
SELSRCA<3:0>
SELSRCA<3:0>
SELSRCA<3:0>
SELSRCA<3:0>
Bit 2
—
—
—
—
CVR<3:0>
Bit 2
—
—
CFDIV<2:0>
CFDIV<2:0>
CFDIV<2:0>
CFDIV<2:0>
C2OUT
Bit 1
AAEN
AAEN
AAEN
AAEN
Bit 1
Bit 1
CCH<1:0>
CCH<1:0>
CCH<1:0>
CCH<1:0>
—
—
—
C1OUT
AANEN
AANEN
AANEN
AANEN
Bit 0
Bit 0
Bit 0
—
—
—
Resets
Resets
Resets
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All