DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 221

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

15.2
REGISTER 15-1:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1:
ENFLTA
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
R/W-0
U-0
—
2:
Output Compare Control Registers
OCxR and OCxRS are double-buffered in PWM mode only.
Each Output Compare module (OCx) has one PTG clock source. See
Generator (PTG) Module”
PTGO4 = OC1
PTGO5 = OC2
PTGO6 = OC3
PTGO7 = OC4
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL<2:0>: Output Compare x Clock Select bits
111 = Peripheral clock (F
110 = Reserved
101 = PTGOx clock
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
010 = T4CLK is the clock source of the OCx
001 = T3CLK is the clock source of the OCx
000 = T2CLK is the clock source of the OCx
Unimplemented: Read as ‘0’
ENFLTB: Fault B Input Enable bit
1 = Output Compare Fault B input (OCFB) is enabled
0 = Output Compare Fault B input (OCFB) is disabled
ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled
0 = Output Compare Fault A input (OCFA) is disabled
Unimplemented: Read as ‘0’
OCFLTB: PWM Fault B Condition Status bit
1 = PWM Fault B condition on OCFB pin has occurred
0 = No PWM Fault B condition on OCFB pin has occurred
OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on OCFA pin has occurred
0 = No PWM Fault A condition on OCFA pin has occurred
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
U-0
U-0
—
—
OCxCON1: OUTPUT COMPAREx CONTROL REGISTER 1
HCS = Hardware Clearable/Settable bit
W = Writable bit
‘1’ = Bit is set
R/W-0 HCS
OCFLTB
OCSIDL
R/W-0
(2)
for more information.
P
)
R/W-0 HCS
OCFLTA
R/W-0
OCTSEL<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRIGMODE
R/W-0
R/W-0
R/W-0
R/W-0
Section 24.0 “Peripheral Trigger
x = Bit is unknown
OCM<2:0>
R/W-0
U-0
—
DS70657F-page 221
ENFLTB
R/W-0
R/W-0
bit 8
bit 0