DSPIC33EP128MC504-I/ML Microchip Technology, DSPIC33EP128MC504-I/ML Datasheet - Page 320

• Manufacturer Part Number: DSPIC33EP128MC504-I/ML
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/ML

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

FIGURE 23-1:
This diagram depicts all of the available
ADC connection options to the four S&H
amplifiers, which are designated: CH0,
CH1, CH2, and CH3.
The ANx analog pins or op amp outputs
are connected to the CH0-CH3 amplifiers
through the multiplexers controlled by the
SFR
CH123Sx and CH123Nx.
Note
PGED3/V
Control
PGEC3/V
1:
2:
3:
4:
V
Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
These bits can be updated with Step commands from the PTG module. See
When ADDMAEN (ADxCON4<8>) = 1 enabling DMA, only ADCxBUF0 is used.
REF
REF
bits,
REF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
+, V
+/AN3/OA1OUT/RPI33/CTED1/RB1
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN8/C3IN1+/U1RTS/BCLK1/RC2
PGEC1/AN4/C1IN1+/RPI34/RB2
CH0Sx,
REF
PGED1/AN5/C1IN1-/RP35/RB3
ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
- inputs can be multiplexed with other analog inputs.
AN11/C1IN2-/U1CTS/RC11
AN7/C3IN1-/C4IN1-/RC1
CHONx,
AN0/OA2OUT/RA0
AN10/RPI28/RA12
AN1/C2IN1+/RA1
AN9/RPI27/RA11
CTMU TEMP
OA1-OA3
AN0-ANx
OPEN
CMP1
+
/OA1
–
+
–
+
–
+
–
OPMODE
OPMODE
OPMODE
OA1
V
V
REFL
REFL
OA3
OA2
V
REFL
CH123x
CH0Sx
0
1
00000
11111
CH123Sx
CH123Sx
Section 24.0 “Peripheral Trigger Generator (PTG) Module”
V
0
1
REFL
0
1
CH123Nx
CH123Nx
CH123Nx
CH0Nx
0x
10
11
0
1
0x
10
11
0x
10
11
+
CH1
–
+
–
CH0
+
–
CH2
+
–
CH3
Current Source (CTMUI)
S&H1
S&H0
S&H2
S&H3
From CTMU
V
Channel Scan
REF
for more information.
+
(1)
V
CH123NA<2:0>
CH123NB<2:0>
CH0SA<4:0>
CH0SB<4:0>
REFH
AV
CH123SA
CH123SB
ALTS
VCFG<2:0>
CH0NA
CH0NB
DD
SAR ADC
V
(3)
(3)
(3)
(3)
REF
CSCNA
V
-
(MUXA/MUXB)
REFL
0
1
Alternate Input
(1)
Selection
AV
SS
A
B
A
B
A
B
A
B
ADC1BUFE
ADC1BUFF
ADC1BUF0
ADC1BUF1
ADC1BUF2
CH0Sx
CH0Nx
CH123Sx
CH123Nx
(4)
(4)
(4)
(4)
(4)